Denon D-MA5DV - Page 30

D-MAS5DV/D-MX7700DV
UPD70F3033AY(IC251)
@ UPD70F3033AF te sEX
[PinNO.
|
Pin
Name
Act
VO
Description
1
FU_DA
H/L
0
FUNCTION
1C(NJU7313AU)
DATA
2
FU_CLK
H/L
0
FUNCTION
IC
(NJU7313AU)
CLOCK
3
-
-
-
NOT
CONNECTED
4
VR_DA
H/L
0
VOLUME
1C(LC75343M)
DATA
5
VR_CLK
H/L
0
VOLUME
1C(LC75343M)
CLOCK
6
-
=
-
NOT
CONNECTED
y]
FLD_DO
H/L
0
FL
DRIVER
1¢(M66005)
DATA
8
FLD_CLK
H/L
0
FL
DRIVER
1C(M66005)
CLOCK
9 EVdd |
Hof
EVss_
ND
FOR
PORT
s—“s~s~S™SCSCSY
fii
[FLDRESET
(LT
FL
DRIVER
IC(W66005)
RESET
—iC(‘*C*”’
2
[FUDGE
DRIVER
TC(W66005)
CE
—Ci‘s~S™S
13
RWCO
TT
TREMOTE
CONTROL
SENSOR
INS
40
VRE
VOLUME
TCCEC75343m)
CES”
[5
——S«[MD_DALOUT
=
~~«STH/L__[0
|
MD
MECHA
DATA
OUTPUT
UART
INTERFACE)
‘16
STMDDALIN.
=~—S——~—~C—é“‘;~‘~*TL~S«&S'TT.~_
|
MD
MECHA
DATA
INPUT
UART
INTERFACE)
7
MD_CLK
/L
0
MD
MECHA
CLOCK
lym
HP_DET
HEAD
PHONE
INPUT
CHECK
(IN=LOW)
=
NOT
CONNECTED
NOT CONNECTED
FLASH WRITE VPP
MD MECHA CE
MD MECHA RESET (RESET=HI GH)
TUNER PLL IC (LC72131) CE
TUNER PLL IC (LC72131) DATA OUTPUT
TUNER PLL IC (LC72131) CLOCK
TUNER PLL IC (LC72131) DATA INPUT
TUNER PLL IC (LC72131) STEREO INPUT
TUNER PLL IC (LC72131) TUNE INPUT
NOT CONNECTED
NOT CONNECTED
NOT CONNECTED
OPTICAL OUTPUT ON/OFF (ON=LOW)
CPU RESET
32. 768kHz (SUB CLOCK)
32. 768kHz (SUB CLOCK)
REGULATOR CONTROL
20MHz (MAIN CLOCK)
20MHz (MAIN CLOCK)
GND
POWER SUPPLY
NOT CONNECTED
FM BEAT CUT
FLASHROM MODE
MD_STB
MD_RESET
TU_CE
TU_DO
TU_CLK
TU_DATA
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