Denon D-MA5DV - Page 40

D-MA5DV/D-MX7700DV 40
Sub-beam addition signal input
Phase detector reference current generator. Connect a resistor between this pin and
ground to set reference current
Frequency detector reference current generator. Connect a resistor between this pin and
ground to set reference current
Data PLL loop filter pin#2
Output node of frequency detector charge pump circuit
Input node of loop filter OP circuit
PLL reference voltage input
Phase detector filter pin#1
O/ Reference voltage output
/A___| Auto Wide Range Control of VCO input pin. For enlarge VCO range in CAV mode
Detect detection signal input
Chip select signal for accessing control registers
Clock output for accessing control registers
/O __| Registers data input/output pin
Laser diode on/off control output for both CD/DVD
Motor Hall sensor input
Spindle motor on output
These pins are used to monitor some status of servo control block
XSSBAD
XSPDIREF VA
tw
167 XSFDIREF VA
XSPLLFTR2 i
XSFDO
XSFTROPI
XSVR_PLL
XSPDOFTR2
XSVREFO
XSAWRCVCO
XSDFCT
XSCSJ
XSCLK
XSDATA
XSLDC
XSFGIN
XSSPDON
XSFLAG[3:0]
171
>
—_— =/=—/</O/—
36, 37, 38, 39
B[ALA Feed Feed Cord Kot) fe) re ard rd ed Bl] o@)= O11 =/S/16] NIN] NIN
TERT
1. These pins are used as general purpose I/O bus
48,
51,
52
2.
When
les
internal
inicyoonirellen
XGPIO
2]
can
be
used
as
programmable
I/O
port
3.6.
\/O _| Internal microcontroller programmable /O port 1.6.
This pin is now changed to be NC.
Internal microcontroller programmable /O
VO _| internal microcontroller programmable I/O port 1.3.
i
Internal microcontroller programmable I/O port 1.2.
Internal microcontroller programmable I/O port 1.1.
Internal microcontroller programmabie I/O port 1.0.
This pin is default used as the A16 (microcontroller address line 16
XMFSCSJ /O _| Output chip select connected to external flash ROM chip enable pin
/ Output program store enable connected to external ROM PSEN4J pin.
XMPSENJ
XMALE VO _| This signal is used as address latch signal in address/data mux mode
1. This signal must be asserted for all microcontroller accesses to the register of this chip
XMCSJ
2.
When
use
internal
microcontroller,
this
signal
can
be
used
as
programmable
I/O
port
3.1
1. This signal is used as the Read Strobe signal
XMRDJ
2.
When
use
internal
microcontroller,
this
signal
can
be
used
as
programmabie
I/O
port
3.0
XMWRJ This signal is used as the Wire Strobe signal
T v0 1. This signal is an interrupt line to the microcontroller
XMINT1J 2. When use internal microcontroller, this signal can be used as programmable I/O
XMP1_2
XMP1_1
XMP1_0
>
i
a N
g
re)
N
o
3 [3
~“
nN
N N
ENR) =
NSN
a
N “N “I
©
x
fe) o S
N
79, 80, 81, 82,
83, 84, 85, 86, XMA[15:0] VO | These pins are used as address bus
87, 89, 90, 91
62,
63,
64,
65
:
These
pins
are
used
as
data
bus
for
the
16-bit
processor
mode,
or
the
address/data
mux
66,
67,
68,
69
|
XMD[7:0]
vO
bus
for
the
8-bit
processor
mode.
1
163
|
XTPLCK
|
VO
_|PLCKtestpin
On
™—CCOCSC#C#d¥
XTSLRF
|
MO:
SLAP
Wet
pin
ee
POG. =~ =|
60
«|
XOSC2
[Crystaloutput
OT
C—“CSCSCSCSCsdCY
Chip Reset.
As
asserted
low
input
generates
a
component
reset
that
stops
all
operations
within
XCRSTJ
the
chip
and
deasserts
all
output
signals.
All
input/output
signals
are
set
to
input.
XHCStJ This pin is used to select the command block task file registers
193
XHIORJ Asserted by the host during a host I/O read operation
XHIOWJ peration
1. DMA request. This pin is configured as the DMA request signal, and is used during DMA transfer
XHDRQ
between
the
host
and
the
controller.
This
pin
is
tri-stated
when
DMA
transfers
are
not
enabled.
2. MPEG acknowledge. This pin is used as the ACKJ signal when MPEG interface mode is selected.
1. DMA acknowledge. This pin is configured as DACKJ, and is used as the DMA acknowledge
signal during DMA data transfers.
2. MPEG request. This pin is used as the REQ signal when MPEG interface mode is selected
1. 16-bit data select. This signal indicates that a 16-bit data transfer is active on the host data
bus. This pin is open-drain tri-state output.
2. MPEG clock. This pin is used as the CLOCK sig
XHRSTJ |__| | Host Reset. The reset of ATA bus
1.
Host
interface
request.
This
tri-state
pin
is
the
host
interrupt
request,
and
is
asserted
to
indicate to the host that the controller needs attention.
2. MPEG begin. This pin is used as the BEGIN signal when MPEG interface mode is selected
bole
ie |
ms
XHCS3J |_| | This pin is used to select the control block task file registers
| ||
re
101 XHDACKJ
XHCS16J
nal when MPEG interface mode is selected.
XHINT
a
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