Denon D-MA5DV - Page 41

D-MASDV/D-MX7700DV
HPDIAGJ This pin is used as the Passed Diagnostics signal, and may be an input or an open-drain output
This pin is used as the Drive Active/Slave Present signal, and is an input or an open-drain
XHDASPJ vO output. This pin is used for Master/Slave drive communication and/or for driving an LED
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1. /O channel ready. This signal is driven low to extend host transfer cycles when the controller
XHIORDY vO is not ready to respond. This pin will be tri-stated when a read or write is not in progress.
2. MPEG error. This pin is used as the ERROR signal when MPEG interface mode is selected
Host address lines. The host address lines A[2:0] are used to access the various host control,
status, and data registers
1. Host data bus. This bus is used to transfer data and status between the host and the controller.
2. MPEG data bus 7-8. The HD[7:0] are used as the DATA [7:0] when MPEG interface mode is selected.
3. VCD I/F. Bit3-0 are used as VCD I/F signal when VCD function is enabled. The relationship of
1
02
95,96,98 | XHA[2:0] La |
106, 107, 108,
109, 111, 112,
113, 114, 116,
bit3-0 and VCD I/F is as follow
117, 118, 119, | XHD[15.0] vO HDO—CD-DATA
120, 121, 122, HD1—CD-LRCK
123 HD2—CD-BCK
HD3—CD-C2PO
| O | This signal is the clock output for SDRAM
This signal is used as the memory output enable for external DRAM buffers. After RSTJ is
asserted, this signal will be low
5
This signal is asserted low when a buffer memory write operation is active
| Oo |
rn This signal is used as Row address output to external DRAM buffer. After RSTJ is asserted, this
signal will be high
This signal is used as column address output to external DRAM. After RSTJ is asserted, this
signal will be high
1. RAM address lines. These are bits11-0 for addressing the buffer memory.
2. Hardware setting. The bits6-0 are used as hardware setting for some functions.
RA{9] : FLASH size is 64K/128K
1: FLASH size is 64K
0: FLASH size is 128K
RA{8] : External CPU is 8032/H8
1: 8032
0: H8
RA[7] : Microcontroller programmable I/O port 1 pin control
1: By internal microcontroller
0: By registers to decide input/output
RA[6] : System test pin output
1: Normal operation
0: System test pin output
RA|[5] : For testing purpose, don’t need to set
RA[4] : IDE master/slave
1: Slave
0: Master
RA[3] : For testing purpose, don’t need to set
RA[2] : For testing purpose, don’t need to set
RA[1-0] : MCU Mode selection
11: Normal Mode (internal uP, internal address latch)
10: Outside uP Mode (ICE Mode)
01: Test mode for internal uP testing
00: Internal uP mode with external address latch
143
147
142
144
145
148, 149, 151,
152, 153, 155,
156, 157, 158,
159, 160, 161
XRA[11:0}
124, 125, 126,
127, 128, 129,
131, 132, 134, XRDI15: : ‘ .
135, 136, 137, [15:0] VO | These signals are the 8-bit parallel data lines to/from the buffer memory.
138, 139, 140,
141
p4 CS LAVDDS_DS_ [Analog Power+5VforDataSlicerpart Cd
[ [Analog Power+5VforDACpartSSOSC~—SSCSCSCSC‘“‘<‘<‘<;CSCSt*
AVDDS_AD_ | _[AnalogPower+5VforADC part C—C(‘“CSC*SCSCSCSC‘*d”
AVDD5_PL |__| Analog Power +5V for Data PLL part
115, 146, VDD Power +3.3V for digital core logic and pad
150, 162
(1 —~—~—~—~«{AVSS_DS__—_{__| Analog Ground for Data Slicer part
p16 CAVSS_DA |__| Analog Ground for DAC part
| 22 CJAVSS_AD |__| Analog Ground for ADC part
1170 ~~=~——Ss[AVSS_PL_—s{_—_| Analog Ground for Data PLL part
88, 110, 130, | GND Digital Ground core logic and pad.
138, 154, 165
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