Denon D-MA5DV - Page 43

D-MASDV/D-MX7700DV 43
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SIGO Bottom Envelope Output. Bottom envelope for mirror detection
Defect Output. Pseudo CMOS output. When a defect is detected, the DFT output goes high. Also
the servo AGC output can be monitored at this pin, when CAR bits 7-4 are ‘0011’
Pull-in Signal Output. The summing signal output of A, B, C, D or PD1, PD2 for mirror detection.
Reference to VCI
DVDLD APC output. DVD APC output pin to control the laser power
CDLD | o | APC output. CD APC output pin to control the laser power
[so —s—«s(BYP.t~‘“‘COC*O@UL#«COC The RF AGC integration capacitor CBYP, is connected between BYP and VPA
fo foe | wo | Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
the CN pin
Differential Phase tracking LPF pin. An external capacitance is connected between this pin and
1 a the CP pin
Center Error LPF pin. An external capacitance is connected between this pin and the LCN pin
Center Error LPF pin. An external capacitance is connected between this pin and the LCP pin
| — |
| — |
| —__|MIRR signal Peak hold pin. An external capacitance is connected to between this pin and VPB_|
| —__|MIRR signal Bottom hold pin. An external capacitance is connected to between this pin and VPB_|
| — | Sigo Bottom Envelope pin. An external capacitance is connected to between this pin and VPB_|
sg _sebre: ——— J | CD Tracking. E-F Opamp output for feedback
| — |
| —_|
PI Top Hold pin. An external capacitance is connected to between this pin and VPB
Reference Voltage output. This pin provides the internal DC bias reference voltage (+2.5V lix).
Output Impedance is less than 500hms
Reference Voltage input. DC bias voltage input for the servo input reference
Reference Voltage input. DC bias voltage input for the servo input reference
Serial Data Enable. Serial Enable CMOS input. A high level input enable the serial port (Not to be
left open
Serial Data. Serial data bi-directional CMOS pin. NRZ programming data for the internal registers
is applied to this input ( Not to be left open
Serial Clock. Serial Clock CMOS input. The clock applied to this pin is synchronized with the data
applied to SDATA (Not to be left open
Ea ee ee Power. Power supply pin for the RF block and serial port
je sivpB | Power. Power supply pin forthe servoblock
jo |vNA | Ground. Ground pin forthe RF blockandserialpot
p20 ive | Ground. Ground pin forthe servo bolk
VO
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