Denon D-MA5DV - Page 44

D-MASDV/D-MX7700DV 44
HY57V65120BTC-75 (ME: U11)
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28
PIN DESCRIPTION
The system clock input. All other inputs are registered to the SDRAM on the
CLK Clock a
rising edge of CLK
Controls internal clock signal and when deactivated, the SDRAM will be one
CKE Clock Enable
of the states among power down, suspend or self refresh
Chip Select Enables or disables all inputs except CLK, CKE and DQM
Selects bank to be activated during RAS activity
ener
BRU
earess
Selects
bank
to
be
read/written
during
CAS
activity
AO~
At
Adarees
Row
Address
:
RAO
~
RA11,
Column
Address
:
CAO
~
CA7
Auto-precharge flag : A10
Row Address Strobe, Way eS ;
RAS,
CAS,
WE
|
Column
Address
Strobe,
BUNS,
ofS
and
WE
denne
the
operation
é Refer function truth table for details
Write Enable
LDQM,
UDQM
Data
Input/Output
Mask
Controls
output
buffers
in
read
mode
and
masks
input
data
in
write
mode
DQO ~ DQ15 Data Input/Output Multiplexed data input / output pin
Power Supply/Ground Power supply for internal circuits and input buffers
Data Output Power/Ground Power supply for output buffers
i
No connection