Denon D-MA5DV - Page 45

D-MASDV/D-MX7700DV
T431616A-8S(ME:U5)
DQI5
pai4
Dai3
DQ12
50
49
48
47
46
45
44
43
42
4
40
39
38
37
36
3
34
33
32
31
30
2
28
27
26
PIN DESCRIPTION
System Clock Active on the positive going edge to sample all input
=e : Disables or enables device operation by masking or enabling all input
Chip Select
Masks system clock to freeze operation from the next clock cycle.
CKE Clock Enable CKE should be enabled at least one cycle prior to new command.
Disable input buffers for power down in standby.
BA
RAS
CAS
WE
AO ~ A10/AP Row/column aaddresses are multiplexed on the same pins.
Row address : RAO ~ RA10,column address : CAO ~ CA7
Select bank for read/write during column address latch time.
Latches row addresses on the positive going edge of the CLK
Row Address Strobe with RAS low.
Enables row access & precharge.
Latches column addresses on the positive going edge of the CLK
with CAS low.
Enables column access.
Write Enable Enables write operation and row precharge.
Latches data in starting from CAS, WE active.
Makes data output Hi-Z, tsHz after the clock and masks the output.
L(U)DQM Data Input/Output Mask Blocks data input when L(U)DQM active.
DQ0 ~ DQ15 Data Input/Output Data inputs/outputs are multiplexed on the same pins.
Power Supply/Ground Powe and ground for the input buffers and the core logic.
tsolated power supply and ground for the output buffers to provide
NC/RFU No Connection/Reserved This pin is recommended to be left No Connection on the device.
: for Future Use
Column Address Strobe
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