Denon D-MA5DV - Page 46

D-MA5DV/D-MX7700DV
MX29LV800BTC-70 (ME: U10)
AS 1 48 A16
At4 =] 2 C) 47 |. BYTE
A13 3 46 [7 GND
A12 4 45 [> Q15/A-1
AM U1 5 44 | Q7
A10 <1 6 43 Q14
AS 17 42 as
AB 8 41 f= 13
40 Qs
39 [= a12
38 [2 a4
RESET = 37 [> vec
36 f= ant
35 = 3
RY/BY 34 ato
33 fo: a2
32 [> a9
31 [= at
30 f= as
29 |= ao
2a [> OF
27 [= GND
26 [| CE
25 | ao
BLOCK DIAGRAM
CONTROL PROGRAM/ERASE
INPUT HIGH VOLTAGE
Logic MACHINE
(WSM)
STATE
REGISTER
ADDRESS FLASH
LATCH ARRAY
AND
x
Ysqdo0o030
4aqg0o0aG-
COMMAND
DATA
BUFFER
y
COMMAND
DATA LATCH
DATA LATCH
Q0-Q15/A-1 = (0 BUFFER
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