Denon DN-C680 - Page 16

16
16DN-C680
MN662724 (MA: IC114)
MN662724 Terminal Function
Pin No. Symbol I/O Function
1 BCLK O Bit clock output for SRDATA.
2 LRCK O L,R discrimination signal output.
3 SRDATA O Serial data output.
4 DVDD1  Power supply for digital circuit.
5 DVSS1  GND for digital circuit.
6 TX O Digital audio interface output signal.
7 MCLK I Microcomputer command clock signal input (latches data at rising edge).
8 MDATA I Microcomputer command data input.
9 MLD I Microcomputer command load signal input. ("L": load)
10 SENSE O Sens signal output (OFT, FESL, NACEND, NAJEND, POSAD, SFG).
11 FLOCK O Focus servo draw in signal ("L": draw in state).
12 TLOCK O Tracking servo draw in signal ("L": draw in state).
13 BLKCK O Subcode block clock signal (fBLKCK=75Hz).
14 SQCK I External clock input for subcode Q register.
15 SUBQ O Subcode Q code output.
16 DMUTE I Muting input ("H": mute).
17 STAT O Status signal (CRC, CUE, CLVS, TTSTOP, FCLV, SQOK).
18 RST I Reset input ("L": reset).
19 SMCK O 8.4672MHz clock signal output at MSEL="H". 4.2336MHz clock signal output at MSEL="L".
20 PMCK O 88.2kHz clock output.
21 TRV O Traverse forcible sending output. 3-state.
22 TVD O Traverse drive output.
23 PC O Spindle motor ON signal ("L": ON).
24 ECM O Spindle motor drive signal (forcible mode output). 3-state.
25 ECS O Spindle motor drive signal (servo error signal output).
26 KICK O Kick pulse output. 3-state.
27 TRD O Tracking drive output.
28 FOD O Focus drive output.
29 VREF I Reference voltage for DA output portion (TVD,BCS,TRD,FOD,FBAL,TBAL).
30 FBAL O Focus balance adjusting output.
31 TBAL O Tracking balance adjusting output.
32 FE I Focus error signal input (analog input).
33 TE I Tracking error signal input (analog input).
34 RFENV I RF envelope signal input (analog input).
35 VDET I Vibration detecting signal input ("H": detect).
60
61
8
0
1
20
21
40
41