Denon DN-C680 Service Manual

9
9DN-C680
29 A7 A7 O - - Unfix - Address bus
30 A8 A8 O - - Unfix - Address bus
31 A9 A9 O - - Unfix - Address bus
32 A10 A10 O - - Unfix - Address bus
33 A11 A11 O - - Unfix - Address bus
34 AVdd AVdd - - - - - Analog power supply(+3.3V)
35 A12 A12 O - - Unfix - Address bus
36 A13 A13 O - - Unfix - Address bus
37 A14 A14 O - - Unfix - Address bus
38 A15 A15 O - - Unfix - Address bus
39 A16,P40 A16 O - - Unfix - Address bus
40 A17,P41 A17 O - - Unfix - Address bus
41 A18,P42 A18 O - - Unfix - Address bus(Not used.)
42 A19,P43 A19 O - - Unfix - Address bus(Not used.)
43 VREF- VREF- - - - - - Analog reference voltage supply
44 A20,P44,AN4 A20 O - - Unfix - Address bus
45 A21,P45,AN5 A21 O - - Unfix - Address bus
46 A22,P46,AN6,STOP CCLK O - - - H FL DRIVER(M66005),LED DRIVER(NJU3713),PARALLEL
DRIVER(NJU3715) control signal:Clock
47 A23,P47,AN7,WDOUT CDAT O - - - H FL DRIVER(M66005),LED DRIVER(NJU3713),PARALLEL
DRIVER(NJU3715) control signal:Data
48 P80,TMI40A -LDC I - - - - FPGA(XCS05XL) control signal:Ldc(not used)
49 P81,TMI40B DONE I - Pu L - FPGA(XCS05XL) control signal:Done
50 P82,TMOIO,SBT3,
SCL3,SBI2
-PSTB0 O - Pu H H NJU3713 control signal:Strobe
51 P83,TM4IO,SBI3 SYSRSTO O - Pu H - System reset output 'L':Reset
52 P84,TM7IO,SBO3,SDA3 TRCL0 O - - - H DIT(YM3437C) control signal:Strobe
53 P85,TM9IOA,SBT4,
SCL4,SBO2
TRCL1 O - - - - FPGA(XCS05XL) initialize status
('L':While initializing,'H':Operation(*1))
54 VREF+ VREF+ - - - - - Analog reference voltage supply
55 P86,TM9IOB,SBI4 RXD I - Pu H - Serial port(Receive)
56 P87,TM9IC,SB04,SDA4 TXD O - - - - Serial port(Transmission)
57 P90,TM8IOA,BIBT1,
-DMAREQ1
SUBQ I - Pu H - DSP(MN662724) subcode data input
58 P91,TMIOIOA,BIBT2,
-DMAACK1
SENSE I - Pu H - DSP(MN662724) servo status input
59 P92,TMIOIOB,
-DMAREQ0
-FLOCK I - Pu H - DSP(MN662724) status input 'L':focus on
60 P93,TMIOIC,
-DMAACK0
-TLOCK I - Pu H - DSP(MN662724) status input 'L':tracking servo on input
61 AVss AVss - - - - - Analog GND(0V)
62 P94,AN0 STAT I - Pu H - DSP(MN662724) status input
63 P95,AN1 SQCK O - - - H DSP(MN662724) control signal:SQCK(subcode read clock)
64 P96,AN2 -INIT I - Pu H - FPGA(XCS05XL) control signal:Init
65 P97,AN3 -PGM O - Pu H - FPGA(XCS05XL) control signal:Program
66 Vdd VDD - - - - - Power supply(+3.3V)
67 P70,SBT0,-RAS MDAT O - - - - DSP(MN662724),DAC(PCM1738) control signal:Data
68 P71,SBIO,-LCAS,-CAS -CSEN O - Pu H H KEY MATRIX(74HC138) control signal:enable
69 P72,SBD0 -PRST O Lv Pd L - Round IC reset signal
70 P73,SBT1,DMUX CCLK O - - - - FPGA(XCS05XL) control signal:Clock
71 P74,SBI1 MCLK O - - - - DSP(MN662724),DAC(PCM1738) control signal:Clock
72 P75,SBO1 SPDATA O - - - - FPGA(XCS05XL) control signal:Data
73 PULLUP PULLUP I - Pu H - Pull up 33-50K
74 PULLUP PULLUP I - Pu H - Pull up 33-50K
75 -NMI -NMI I - Pu H - Not used. Open
76 PA0,-IRQ0 BLKCK I Ed Pu - - DSP(MN662724) subcode input(interrupt)
77 PA1,-IRQ1 RFDET I Ed Pu H - DSP(MN662724) HF detect signal(not used)
Pin
No.
Port Name Symbol I/O DET Ext Res Ini Note

Denon DN-C680 Specifications

General

Brand	Denon
Model	DN-C680
Category	CD Player
Language	English