Denon S-81 - Specifications; Component Specifications

34
S-81/S-81DAB
TC94A14FAG (IC307 : 1U-3760)
Pin Functions
Pin No. Symbol I/O Function Description Remarks
1BCK
O
3-5I/F
Bit clock output pin. 32fs, 48fs, or 64fs selectable by command.
Normal speed:
32fs ı 1.4112 MHz
2 LRCK
O
3-5I/F
L/R channel clock output pin. “L” for L channel and “H” for R
channel. Output polarity can be inverted by command.
Normal speed: 44.1 kHz
3AOUT
O
3-5I/F
Audio data output pin. MSB-first or LSB-first selectable by
command.
ˇ
4 DOUT
O
3-5I/F
Digital data output pin. Outputs up to double-speed playback. Based on CP-1201
5IPF
O
3-5I/F
Correction flag output pin. When set to “H”, AOUT output cannot
be corrected by C2 correction processing.
Alias: C2PO
6V
DD3
ˇ Digital 3.3 V power supply voltage pin. ˇ
7V
SS3
ˇ Digital GND pin. ˇ
8SBOK
O
3-5I/F
Subcode Q data CRCC result output pin. “H” level when result is
OK.
ˇ
9CLCK
I/O
3-5I/F
Subcode P-W data read clock I/O pin. I/O polarity selectable by
command.
Schmitt input
10 DATA
O
3-5I/F
Subcode P-W data output pin. ˇ
-
-
-
-
-
-
-
DV
SS3
RO
DV
DD3
DV
R
LO
DV
SS3
ZDET
V
SS5
BUS0
BUS1
BUS2
BUS3
BUC
K
/CCE
/RST
V
DD5
TEZI
TEI
SBAD
FEI
RFRP
RFZI
RFCT
A
V
DD3
RFI
SLCO
A
V
SS3
VCOF
PV
REF
LPFO
LPFN
TMAX
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
XV
DD3
XO XI XV
SS3
TESIN V
DD3
V
SS3
DMO FMO AV
DD3
SEL TEBC RFGC V
REF
TRO FOO
48
32
3347 46 45 44 43 42 41 40 39 38 37 36 35 34
BC
K
LRC
K
AOUT
DOUT
IPF
V
DD3
V
SS3
SBO
K
CLC
K
DAT
A
SFS
Y
SBS
Y
IO0 IO1
PV
DD3
PDO
1 162 3 4 5 6 7 8 9 10 11 12 13 14 15
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
Micro-
controller
interface
Audio out
circuit
Digital output
Correction
circuit
16 k
RAM
Address
circuit
LPF
Sub code
decoder
CLV servo
ROM
RAM
Digital equalizer
automatic
adjustment circuit
Servo control
PWM
A/D
D/A
Data
slicer
VCO
PLL
TMAX
Clock
generator
1-bit
DAC
Synchronous
guarantee
EFM
decoder
=