35
CXD2500AQFP
(IC681)
@CXD2500AQFP
Pin
Function
Table
Pin
,
are
cription
latte
ve
[ee
|i]
Fo.
[1
||
Focus
OK
input
pin.
Used
in
SENS
output
and
the
servo
auto
sequencer.
|
2
|
Fsw
|
o
|
zo
|
Output
filter
switching
output
of
the
spindle
motor.
|
3
|
MON
|
(@)
1,0
|
On-off
control
output
of
the
spindle
motor.
4
(@)
|
4
|
MDP
|
1,Z,0
|
Servo
control
of
the
spindle
motor.
|
5
|
MDS
|
O
|1,Z,0}
Servo
control
of
the
spindle
motor.
|
6
|
Lock
|
oO
|
1,0
|
Samples
GFS
at
460
Hz.
When
GFS
is
“H”,
H
is
output.
L
is
output
when
there
is
Baka
|
8
|
vcoo
;
O
1,0
|
Oscillation
circuit
output
for
analog
EFM
PLL.
|
9
|
vcor|
1
Oscillation
circuit
output
for
analog
EFM
PLL.
fiock=8.6436
MHz.
PiG)
Test
|r
|
Test
pin,
always
grounded.
11}
ppo
|
o
|1,2.0|
For
charge
pump
used
with
analog
EFM
PLL.
[12[
vss
|__|
Ground
“L’,
8
times
in
succession.
fiz7[
vexr{[
o
|
|
Clock
input
fcenrer
from
the
external
VCO
for
varipitch
equals
16.9344
MHz.
/18|
FILO
|
O
[Analog|
Filter
output
(slave
=
digital
PLL)
for
master
PLL.
fig{
Fur
|
1
|
|
Filter
input
for
master
PLL.
|
20| Pco
|
0
|1,20)
Charge
pump
output
for
master
PLL.
fez
[eutv
|
1
[
[VCO
control
voltage
input
for
master,
[23
[Avo
|__|
Analog
supply
(+5
V)
24
RF
eae
EFM
signal
input
[es
|rest2[
1
[|
[Grounded
[es[rests|
1
[
[Gromded
fa7
|
asyo
[0
|
10
[EFM
full-swing
output
(L=Vss
H=Vo)
roa
([resta|
1
|
[Grounded
feo;
xc
[
=
|
30
|
PSSL
za
Switching
input
for
the
audio
data
output
mode.
Serial
output
with
“L”
and
parallel
output
with
“H”.
:
31
|
WDCK
|
o
|
1,0
|
D/A
interface
for
48-bit
slot.
Word
clock
f
=
2Fs.
|
32
|
LRCK
|
O
|
1.0
|
D/A
interface
for
48-bit
slot.
LR
clock
f=
Fs.
[33]
vo
|
|
Pin
;
;
an
re
amb]
YO
Pe
description
DA16
1.0
DA16
(MSB)
output
when
PSSL
=
1.
Serial
data
of
the
48-bit
slot
when
PSSL
=
0.
*~
|
(2s
COMP,
MSB
first.)
|
35
|
DA15
|
O
|
1,0
|
DALS5
output
when
PSSL
=
1.
Bit
clock
of
the
48-bit
slot
when
PSSL
=
0.
DA14
1.0
DA14
output
when
PSSL
=
1.
Serial
data
of
the
64-bit
slot
when
PSSL
=
0.
"|
(2s’
COMP,
LSB
first.)
"a7
[DAIS
|
O
|
10
[DATS
output
when PSSL
=,
Bit
clock
of
the
G4bie
slot
when
PSL=O.
ae
|
DAIZ
|
0
|
1.0
|DA12
output
when
PSSL=1.
LR
clock
of
the
64-bit
slot
when
PSSL=O.
[39
|
Dali
|
©
|
1,0
|
DA11
output
when
PSSL=1.GTOP
output
when
PSSL=0.
|
40
[
Da1o
|
©
|
1,0
|
DA1O
output
when
PSSL=1.XUGF
output
when
PSSL=0.
|
41
|
Daog
|
©
|
1,0
|
DAO9
output
when
PSSL=1.
XPLCK
output
when
PSSL=0.
42
|
DAO
|
0
|
1,0
[DAOS
output
when
PSSL=1.
GFS
output
when
PSSL=0.
OSS
|
43
|
Dao7
|
0
|
1.0
|
DAO7
output
when
PSSL=1.RFCK
output
when
PSSL=0.
|
44
|
Das
|
©
|
1,0
|
DAOG
output
when
PSSL=1.C2PO
output
when
PSSL=0.
PDAS
|
0
|
1.0
|
DAOS
output
when
PSSL=1.
XRAOF
output
when
PSSL=O.OOSOSC~S
46
[
DAO4
|
0
|
1,0
|
DA04
output
when
PSSL=1.
MNT3
output
when
PSSL=0.SSOOSC~S~S
[47
|
Dao3
|
©
|
1,0
|DAO3
output
when
PSSL=1.
MNT2
output
when
PSSL=0.
rae
|
paoz
|
0
|
1.0
[DAO2
output
when
PSSL=1.
MNT!
output
when
PSSL=0.SOSOS~C~S~S
[49
|
DAOL
|
0
|
1,0
|
DAOL
output
when
PSSL=1.
MNTO
output
when
PSSL=0.=SOSC~S~S~S
|50
|
APTR|
O
|
1,0
|
Control
output
for
aperture
correction.
“H”
with
Rch.
151
|
APTL
|
O
|
1,0
|
Control
output
for
aperture
correction.
“H”
with
Lch.
rsa
ves
|
[wma
SC“‘“SC“—*SsS~“s~S~“S~S*S~S
[53
|
xTal
|
1
|
[16.9344
MHz
x'tal
oscillator
circuit
input.
Or
33.8688
MHz
input
[54
[xTAO|
0
|
10
[169944
MHz
wal
oscillator
cireuit
input
SSCS
|
55
|
XTSL
|
1
|
|
X'tal
selection
input
pin.
“L”
when
the
x'tal
is
16.9344
MHz
and
“H”
when
the
x'tal
is
33.8688
MHz.
[56
|
FSTT
|
0
|
1.0
|
2/3
frequency
division
output
of
pins
53
and 54.
Does
not
change
with
vari-piteh,
rs7
|
cam
|
0
|
10
|
42896
Miz
output. Changes
simultaneously
when
varypitch
is
applied
——=SSSS~*Y
58
|
C1eM|
0
|
1.0
|
169344
Mile
output.
Changes
simultaneously
when
varypitch
is
applied
———=SC~*~*~*S~*
so
|
pz
[1
|
|
Digial-Out
on/off
control
H
when
on
and
L
when
off.
—SSSOSC~S~S
(60
[pout]
©
|
10
|Digital-out
output
pin
Csi‘“‘CSCSC‘idC
61
|
EMPH|
O
|
10
|
When
the
playback
disc
has
emphasis,
“H”
is
output.
“L”
is
output
when
there
is
no
emphasis.
|
62
|
wrck|
0
|
1.0
|
WFCK
(Write
Frame
Clock)
outpit
Fea
|
scor
[0
|
10
|-H
output
when
either
sub
code
syne
SO
or
Sib
deed
———OSC~“‘“*~“~*~*~*Y
Fe«[-saso
|
0
|
10
[Sub
P
through
W
seri
ompwt
SS
CCOC“~S*~“~*S*~*™
[es
|
EXCK
|
I
|
|
Clock input
for
SBSO
readout
we
—S—SCSC~—SCSCS
66
[
saso
|
0
|
10
|
Sub@
80
bit
and PCM
peak
level
data
16-bit
output
——SSCSC*C~“~‘“~*S*~“‘*~*~*~*~*S
Fer
[sack
|
1
|
|
Clock input
for
SQSO
readout
we
CC“‘“S*~“‘~‘~*s*~*s*~S*~*~S~*Y
res
[wure[
1
|
[Mute
L
is
canceled
with
SOSOCSCSCSCSCSCSCSC~“~S*S*~S
69
|
SENS
|
—
[1.20]
SENS
output.
Ouput
to
CPU———SSSCSC~“—SC“SsS~“S*S*~—~—~—~S
ro
[xest
|
1
|
|
Svatem
set.
Reset
with
"LSSSOCSC~—CSCSCSC“‘“‘<;
CS
ri
[pata
|
1
|
|
Serial
data
input
from
CPU
SSOSCSC~“S~SC“~S~“S~S~S~SSS
7a
[xtat
|
1
|
[Latch
input
from
CPU.
Latches
serial
data
onthe
fall.
———SOSC~S~*~—~S~S~S
73
|
vo
|
[Sup
(tsWCOC“~sSCS“S*S*S*=“—*S~S~S~S~S
[74
|
GLOK
|
1
[|
Serial
data
transfer
cock
input
om
GPUS
prs
[-sein
[1
[
[Sense
input
fom
SSCS
[76
[
en
[
0
|
|
Count
signal
input
of
aumber
of
wack
imps.
——~—S=SC~“~*~“~*~S*S*S*~S~S~S~«*S
[77
[Dato
|
O10
[Serial
data
ouput
SSP
OSOSCSCSC—~“CS
[7@
[
xu70
[0
|
1.0
|
Serial
data
latch
output
to
SSP.
Latches
on
the
fall
SSCS
[79
[cxxo
[0
[10
[serial
data
transfer
clock
ouput
SSeS
[80
|
MIRR
|
1
|
|
Mirror
signal input.
Used
in
jumps
of
128
tracks
or
more with
an
auto
sequencer,
D-250
CD
PLAYER
SECTION
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