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Digital Equipment pdp11 User Manual

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Table of Contents

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Digital Equipment pdp11 Specifications

General IconGeneral
BrandDigital Equipment
Modelpdp11
CategoryDesktop
LanguageEnglish

Summary

Programming Peripherals

1.1 PROGRAMMING

Explains how peripherals are programmed using memory reference instructions and device registers.

1.2 DEVICE REGISTERS

Details the two types of registers associated with each device: control/status and data registers.

1.2.1 Control and Status Registers

Describes the general form and typical bit assignments in control and status registers for peripherals.

Basic I/O Terminals

2.1 INTRODUCTION

Introduces basic PDP-11 I/O devices: teleprinters, paper tape units, line printers, and card readers.

2.2 TELETYPE

Describes the ASR 33 Teletype, its operation, programming, registers, and specifications.

2.4 HIGH SPEED LINE PRINTER - LPll

Details the LP11 high-speed line printer, its operation, programming, and specifications.

2.5 PUNCHED CARD READER - CRll AND MARK SENSE CARD READER - CMll

Explains the CR11 and CM11 card readers, their operation, programming, and specifications.

Magnetic Tape Options

3.1 DECTAPE TCll/TU56

Describes the DECtape TC11/TU56 dual-transport system, its introduction, operation, and programming.

3.2 MAGTAPE· TMll/TU10

Details the TM11/TU10 magnetic tape system, its introduction, operation, and programming.

Display Terminals

4.2 STORAGE DISPLAY VTOIA

Describes the VT01A storage display unit, its specifications, and operation.

4.3 OSCILLOSCOPE VR01A

Details the VR01A oscilloscope, its specifications, and applications.

4.4 POINT PLOT DISPLAY VR14

Explains the VR14 point plot display, its specifications, and features.

4.5 ALPHANUMERIC VT05 TERMINAL

Describes the VT05 alphanumeric display terminal, its specifications, and capabilities.

Disk Storage Devices

5.1 DISK ALTERNATIVES

Discusses various mass storage alternatives available for PDP-11 users, including fixed-head and moving-head systems.

5.2 DECDISK MEMORY RC11/RS64

Details the RC11/RS64 disk memory system, its introduction, operation, and programming.

5.3 DISK AND CONTROL RFl1/RSll

Explains the RF11/RS11 disk and control system, its introduction, operation, and programming.

5.4 DECPACK DISK CARTRIDGE SYSTEM - RKll·C/RK02, RK03

Describes the DECpack cartridge disk system, its introduction, operation, and programming.

Clocks

6.1 PROGRAMMABLE REAL TIME CLOCK KW11-P

Details the KW11-P programmable real time clock, its introduction, operating modes, and programming.

6.2 LINE TIME CLOCK KW11-L

Explains the KW11-L line time clock, its programming, and specifications.

Bus Extension Options

7.1 INTRODUCTION

Introduces UNIBUS extension options like bus extenders and bus switches for PDP-11 systems.

7.2 BUS SWITCHES DT11·A and DT11·8

Details the DT11-A and DT11-B bus switches, their operation, switch positions, and control.

Communications Options

8.1 COMMUNICATIONS INTERFACES

Overview of DIGITAL's interfaces for PDP-11 communications applications.

8.2 ASYNCHRONOUS LINE INTERFACE DCll

Describes the DC11 series interface for serial asynchronous lines, its operation, and programming.

8.3 AUTOMATIC CALLING UNIT INTERFACE DN11

Explains the DN11 ACU interface for dialing telephone numbers and establishing data links.

8.4 SYNCHRONOUS INTERFACE DP11

Details the DP11 synchronous line interface, its operation, and specifications.

8.5 ASYNCHRONOUS 16-LINE SINGLE SPEED MULTIPLEXER DM11

Describes the DM11 multiplexer, its introduction, operation, programming, and specifications.

8.6 FULL DUPLEX 8-BIT ASYNCHRONOUS LINE INTERFACE UNIT-KL11

Explains the KL11 interface for full duplex asynchronous serial lines, its programming, and specifications.

8.7 ASYNCHRONOUS NULL MODEM H312A

Details the H312A null modem for connecting terminals to computers without modems.

Data Acquisition and Control Options

9.1 LOW LEVEL ANALOG INPUT SUBSYSTEM - AFC11

Describes the AFC11 analog input subsystem for industrial data acquisition.

9.2 ANALOG TO DIGITAL CONVERSION SUBSYSTEM AD01·D

Details the AD01-D subsystem for multichannel analog data acquisition.

9.3 DIGITAL TO ANALOG CONVERSION SUBSYSTEM AAll·D

Explains the AA11-D subsystem for multichannel digital to analog conversion.

9.4 UNIVERSAL DIGITAL CONTROL SUBSYSTEM - UDC11

Describes the UDC11 for industrial digital I/O, its operation, and modules.

UNIBUS THEORY AND OPERATION

1.1 UNIBUS SIGNAL LINES

Details the PDP-11 UNIBUS signal lines, bus transactions, timing, and interfacing.

1.1.1 Data Transfer lines

Explains the bidirectional and unidirectional lines used for data transfer on the UNIBUS.

1.1.1.1 Data Lines (D<15:00>)

Describes the 16 data lines used to transfer information between master and slave devices.

1.1.1.2 Address Lines (A<17:00>)

Explains the 18 address lines used by the master device to select a slave device or memory location.

1.1.1.3 Control Signals

Details the control signals for data transfer operations, master/slave synchronization, and parity checking.

1.1.2 Priority Transfer Lines

Describes the UNIBUS priority transfer lines, including bus request and grant lines.

1.2 DATA TRANSFER BUS TRANSACTIONS

Explains bus activity, interlocking of control signals, and asynchronous data transfer.

1.3 PRIORITY TRANSFER TRANSACTIONS

Details bus control transfer based on priority arbitration logic and device chaining.

1.4 UNIBUS TIMING

Discusses UNIBUS timing restrictions, signal transmission, and delays for data transfer.

1.5 ADDRESS MAPPING

Explains PDP-11 address mapping, reserved locations for traps, interrupts, and device registers.

Interface Circuits and Hardware

2.1 CIRCUITS

Discusses UNIBUS transmission, signal levels, length, and receiver/transmitter circuits.

2.1.1 UNIBUS TRANSMISSION

Describes UNIBUS cable types, impedance, and transmission characteristics.

2.1.2 UNIBUS SIGNAL LEVELS

Explains the standard UNIBUS signal levels and terminology for active states.

2.1.3 UNIBUS LENGTH AND LOADING

Details UNIBUS length limitations and loading constraints, including repeater options.

2.1.4 Bus Receiver and Transmitter Circuits

Shows equivalent circuits for UNIBUS receivers and transmitters and their characteristics.

2.2 UNIBUS INTERFACE MODULES

Describes modules used for UNIBUS interfacing: jumper module, cable, transmitters, and receivers.

2.2.1 UNIBUS Cables

Details UNIBUS jumper modules and Flexprint cable assemblies.

2.2.2 UNIBUS Terminations

Explains the M930 UNIBUS Terminator Module for signal line termination.

2.2.3 UNIBUS Receivers and Transmitters

Discusses UNIBUS driver and receiver modules (M783, M784, M785, M798).

2.2.4 M105 Address Selector Module

Details the M105 Address Selector Module for selecting device registers and controlling bus signals.

2.2.5 M7820 Interrupt Control Module

Describes the M7820 module for making bus requests and generating interrupts.

2.2.5a The M7821 Interrupt Control Module

Explains the M7821 module as a replacement for M7820, improving system performance.

2.2.6 M795 Word Count and Bus-Address Module

Details the M795 module for DMA devices, including counters for data transfers and bus addresses.

2.2.7 M796 UNIBUS Master Control Module

Describes the M796 module for controlling data transfer operations as a UNIBUS bus master.

2.4 PDP-11 INTERFACE HARDWARE

Provides a description of hardware designed for PDP-11 system interfacing.

2.4.1 BB11 Blank Mounting Panel

Details the BB11 Blank Mounting Panel for general interfacing and system unit mounting.

2.4.2 DD11-A Peripheral Mounting Panel

Explains the DD11-A panel for mounting small peripheral interfaces.

Interface Examples

3.1 BASIC INTERFACE

Describes the simplest read/write interface using a storage register and bus gating circuits.

3.2 PROGRAMMED DEVICE INTERFACE

Explains a programmed interface for analog-to-digital converters (ADC).

3.3 INTERRUPT SERVICED INTERFACE

Details an interface with interrupt capability for ADC, allowing concurrent execution.

3.4 DIRECT MEMORY ACCESS (DMA) INTERFACE

Describes the DMA interface for data transfers between devices and memory without processor intervention.

3.5 OUTPUT INTERFACE WITH INTERRUPT CONTROL

Provides an output interface with interrupt control for DAC devices.

3.6 DAC-DMA INTERFACE

Details the DAC-DMA interface for transferring data directly from memory to DAC.

3.7 PDP-11 TO DATA CHANNEL INTERFACE

Presents an interface between PDP-11 UNIBUS and another computer's data channel.

3.8 PDP-11 TO PDP-11 INTERFACE

Describes the interface for PDP-11 to PDP-11 communication, enabling processor interaction.

3.10 DIRECT MEMORY ACCESS INTERFACE (DR11-B)

Explains the DR11-B DMA interface for direct data transfers between UNIBUS and user devices.

PDP 11 DEVICE REGISTERS AND INTERRUPT VECTORS

VECTORS

Lists interrupt vector addresses and their corresponding devices or functions.

DEVICE ADDRESS

Provides a list of device registers and their assigned UNIBUS addresses.

UNIBUS PIN ASSIGNMENTS

TABLE B-1 UNIBUS PIN ASSIGNMENTS (BY PIN NUMBERS)

Details UNIBUS pin assignments based on pin numbers.

TABLE B-2 UNIBUS PIN ASSIGNMENTS (BY SIGNAL NAME)

Lists UNIBUS pin assignments based on signal names.

TABLE B-3 BB11 POWER PIN ASSIGNMENTS

Provides BB11 power pin assignments for system units.

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