starts the
ADC;
tests the
READY
(CONVERSION
COMPLETE) bit until the bit is
set; and then transfers the data from the digital output
line of the
ADC
to the pro-
cessor. A possible sequence
of
instructions to perform this task is given below.
This program selects
an
input, waits
for
the device to complete the conversion,
and then transfers the result to register
4.
READY:
MOV
TSTB
BPL
MOV
INPUT.ADMUX
ADCSR
READY
ADDBR.R4
lSELECT
ANALOG
INPUT
lCHECK
FOR
CONVERSION COMPLETE
lNO.TEST
AGAIN
lYES.OBTAIN
DATA
INPUT
IS
A LOCATION CONTAINING
THE
NUMBER
OF
THE
DESIRED
ANALOG
INPUT
LINE.
A SUBROUTINE
TO
EXAMPJE A
SERIES
OF
INPUTS
MIGHT
BE
',fRITTEN
AS
FOLLO'",S:
MUXSCN:
LOOP:
DONE:
'.olHERE:
MOV
CLR
TSTB
BPL
MOV
CMP
BEQ
INC
BR
RTS
BUFADR.R4
ADMUX
ADCSR
LOOP
ADDBR.(R4)+
ADMUX.#77
DONE
ADMUX
LOOP
R7
;INITIALIZE
DATA
POINTER
;SELECT
INPUT
LINE
ZERO
;CHECK
FOR
CONVERSION COMPLETE
;NO.TEST
AGAIN
;YES.PLACE
DATA
IN
BUFFER
;LAST
LINE?
;YES.GO
TO
DONE
lNO.GO
TO
NEXT
INPUT
;GO
TO
LOOP
;EXIT
FROM
SUBROUTINE
BUFADR
IS
A LOCATION IN
CORE
CONTAINING
THE
ADDRESS
OF
THE
FIRST
WORD
ON
A 64-WORD BUFFER
ADCSR
IS
THE
INTERFACE STATUS REGISTER
ADMUX
IS
THE
MULTIPLEXER REGISTER
ADDBR
IS
THE
DATA
REGISTER
This subroutine is called
by
the instruction:
JSR
R7,
MUXSCN.
The
subroutine in-
itializes general register 4
as
a pointer
to
the buffer; initializes the multiplexer
reg-
ister
to
zero; and sequentially reads the 64 inputs
into
the corresponding buffer
location.
When
each
input
has
been
read once, control returns
to
the calling pro-
gram with the contents of general register 4
as
the address
of
the word after the
last word
of
the buffer.
Since loading the multiplexer register starts operation
of
the device cycle, ADMUX
should
not
be
accessed
as
a destination operand except
by
a
TST,
BIT,
or
CMP in-
struction. In addition, the
INC
ADMUX instruction should follow the CMP instruc-
tion. This avoids initiating unwanted device operation and allows the subroutine
to
be
immediately recalled.
3.3 INTERRUPT SERVICED INTERFACE
The
interface
to
an analog-to-digital converter would
be
more versatile
if it
in-
cluded an interrupt capability.
An
interrupt serviced interface with this capability
can
be
formed simply
by
adding an M7820 Interrupt Control Module and one bit
to one of the registers in 'the programmed device interface described
in
Paragraph
3.2.
The
interrupt serviced 'interface allows the processor
to
concurrently execute in-
structions of another program while the analog-to-digital converter (ADC) per-
forms a cycle
of
operation. The processor responds to a
READY
(CONVERSION
COMPLETE) signal from the
ADC
by
interacting with the device and analyzing the
251
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