Eventide Ultra-Harmonizer H3000 - Page 4

Тһе PELs
The
PELs
are
centered
around
the
Texas
Instruments
TMS32010
DSP
processor
which
use
external
RAM
for
program
memory.
Its
simple
external
/O
port
design
allows
it
to
interface
to
the
global
bus
relatively
easily.
Each
PEL
consists
of
a
TMS32010
along
with
2
K
words
of
16
bit
external
"program"
memory.
Each
processor
also
contains
144
words
of
internal
"data"
memory.
Also,
mapped
into
the
Program
memory
space
of
each
processor
is
a
unique
"boot"
ROM
for
each
of
the
PELs.
The
processors
run
at
18.3
MHz,
yielding
an
instruction
time
of
218
nanoseconds.
At
the
sample
rate
of
44.1
kHz
this
gives
exactly
104
single-cycle
instructions
per
sample
period
for
each
of
the
PELs.
In
the
TMS32010,
most
instructions
operate
in
a
single
cycle,
with
the
exception
of
branch
instructions,
subroutine
calls
and
/О
instructions.
The
processors
are
connected
to
the
global
bus
through
bidirectional
data
buffers.
They
are
only
attached
to
the
bus
during
the
execution
of
an
VO
(IN
or
OUT
in
TMS32010
code)
instruction.
·
Global
Bus
Addressing
The
addressing
of
the
global
bus
is
tied
very
closely
to
the
I/O
port
structure
of
the
TMS32010.
Like
the
TMS320,
the
global
bus
has
8
read
ports
and
8
write
ports,
each
mapped
to
the
various
peripheral
devices
on
the
bus.
The
PELs
gain
access
to
the
global
bus
by
using
the
I/O
instructions
"IN"
and
"OUT.
Since
the
IN
and
OUT
instructions
are
2
cycle
instructions,
all
bus
accesses
require
at
least
two
instruction
cycles.
The
small
number
of
port
addresses
severely
limit
the
number
of
peripheral
devices
allowed
on
the
bus.
This
is
overcome
by
expanding
one
of
the
sixteen
bit
write
ports
into
sixteen
12-bit
ports.
it
is
done
by
decoding
the
upper
four
data
bits
and
using
those
bits
to
address
the
additional
registers.
The
additional
address
space
allows
for
a
number
of
"flag"
type
registers,
interrupt
control
registers,
and
two
frequency
synthesizer
control
registers.
The Host
The
host
processor
is
the
nerve
center
of
the
H3000,
controlling
all
aspects
of
the
machine.
An
8-bit
microprocessor,
the
6809,
is
the
host.
Given
input
from
the
front
panel
and
the
MIDI
control
port,
the
host
controls
the
signal
processors.
This
includes
loading
executable
code
into
each
of
the
PELs,
calculating
and
setting
all
signal
processing
parameters,
and
controlling
analog
input
and
output
levels.
As
great
as
the
responsibilities
of
the
host
are,
they
are
not
very
computationally
intensive.
The
host
has
access
to
the
global
bus,
but
in
a
more
limited
way
than
the
PELs,
The
slower
6809
is
limited
to
one
bus
access
per
sampie
period,
about
once
every
22
microseconds.
With
this
method,
complex
bus
arbitration
is
unnecessary,
while
an
adequate
data
rate
to
the
PELs
can
be
sustained.