Freescale Semiconductor QorIQ LS1043A

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Summary

Chapter 1 Introduction

Acronyms and Abbreviations

Lists and describes acronyms and abbreviations used in the document.

Board Features

Details the specifications and features of the LS1043ARDB.

Block Diagrams

Presents the LS1043A processor block diagram.

Board Drawings

Shows the physical layout of the LS1043ARDB top view.

Chapter 2 Interfaces

DDR Interface

Describes the high-speed DRAM interface with 2 GB DDR4 SDRAM.

IFC Interface

Details the integrated flash controller (IFC) features and clients.

Serial Interfaces

Covers UART, eSDHC, and DSPI serial interfaces.

Ethernet Interface

Explains the two Ethernet controllers (EC1, EC2) and PHY connections.

SerDes Interface

Lists SerDes embedded devices and protocol combinations.

USB Interface

Describes the three integrated USB 3.0 controllers and architecture.

I2 C Interface

Details the I2C bus device addresses and connections.

Chapter 3 Power Supplies and CPLD Controller

Power Supply Block Diagram

Illustrates the LS1043ARDB power supply block diagram.

Power Supply Operation

Explains the power ON and power sequencing activities.

CPLD Controller

Describes the complex programmable logic device (CPLD) controller functions.

Power-On Reset

Shows the timing diagram of the power-on reset (POR) sequence.

DDR Supply

Lists the voltage and current for the DDR4 interface.

POVDD Supply

Explains how POVDD power line connects to PROG_MTR and PROG_SFP pins.

Chapter 4 Clocks, Interrupts, and Temperature Monitoring

Clocking Scheme

Presents the LS1043ARDB clocking scheme.

Clock Frequency Selection

Details SYSCLK frequency selection based on SW3 switch settings.

MPIC Controller

Lists the LS1043A interrupt assignments.

Temperature Anode and Cathode

Describes temperature measurement using thermal monitor.

Chapter 5 Debug and Input;Output

ARM;JTAG Architecture

Shows the ARM/JTAG architecture.

CMSIS-DAP

Describes the MBED circuit for serial and debug communications.

GPIOs

Details GPIO mapping and primary functions.

Chapter 6 CPLD Programming

CPLD Memory Map; Register Definitions

Shows the memory map for CPLD registers and their fields.

Appendix A Revision History