Section 4
4-25
4.3.2.4. Analog Interface
Address decoder U27 and PAL U28 provide the address decoding and read/write
controls for the I/O latches. U23, U24, and U25 form a 24-bit Input Latch, which
receives the serial data from the 12-bit ADC on the A/D Converter PCB. The serial
data and clock from the ADC are coupled through the optocoupler U11. U26 is the
Output Latch for Input and Range Selection Control data that is sent to the
Amplifier/Attenuator PCB.
Counter U30 and PAL U8 provide the clocking signals to transmit the data through
the optocoupler U13, to the Input Amplifier PCB. U12 transmits the Charge
Balance Counter Clock and the Status signal. The Status signal is fed to U29 to
generate a processor interrupt.
4.3.2.5. Central Processing Unit
The nanovolt detector CPU is an Intel 80188 processor and the design is similar to
most 80188 CPU designs. The following sections describe the major functional
blocks, however a detailed timing analysis is far beyond the scope of this manual.
If a problem is suspected in this section then checking the subsystems in the order
which they are presented is recommended.
Clock Generation: Crystal X1 provides 14.74 MHz signal to the processor U5,
which generates the system clock (CLK) pin 56. Flip-flop U10 is used to generate
CLK/2 and CLK/4.
Control Signal Generation: The 80188 CPU (U5) contains the required logic to
generate, read, and write strobes for the memory and input/output devices. During
normal system operation the RD signal (Pin 62) should show the most activity,
since the processor should be continually fetching instructions from the program
ROM. The WR signal (Pin 63) should toggle at a rate less than the RD signal and
show a reasonable amount of activity as the processor writes to RAM.
Address And Data Buffers: Addresses from the CPU cluster are latched by the 2
octal latches U1, and U19. This latching operation demultiplexes the address/data
bus of the CPU cluster into separate address and data busses for the peripherals
components. Integrated circuit U16 is an octal bi-directional buffer which transfers
data from the peripheral circuitry to the CPU cluster and vice versa.
Memory And I/O Address Decoding: The CPU (U5) performs all memory and
address decoding internally. The memory chip selects are UCS (for the ROM), LCS
(for the RAM), and the MCS0-3 for other memory devices. The I/O chip selects are
PCS0-6 for the various I/O devices.
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