Section 4
4-26
Interrupt Controller The system Interrupt Controller is within the CPU IC (U5)
and interrupt priorities are set by software.
4.3.2.6. Memory
The Memory section of the CPU PCB consists of 3 general purpose 28 pin sockets
which will allow up to 192 kbytes of ROM with 32 kbytes of RAM, or 96 kbytes of
RAM with 64 kbytes of ROM, or a number of intermediate compromises. In
addition the memory includes an 8 section piano switch which can be used to select
various factory options.
Option Switches: Switch Bank SW1 contains 8 switches which can be gated onto
the bus by U7 when the processor reads the appropriate input/output port.
Memory Sockets: U20 contains a Smart Watch (which has a real time clock and
battery backup for the RAM). Integrated circuit U9 is configured to be ROM since
the processor performs its boot from location 0xFFFF0, and U17 is configured as
RAM.
4.3.2.7. Serial Fibre-Optic Communication Interface.
The serial fibre-optic communication interface section contains an interface to the
main 6675A controller cpu assembly.
4.3.2.8. Gpib Interface.
The GPIB interface is built up from a 68488 controller IC (U6) and two buffers (U3
and U4). U2 inverts the polarity of the interrupt output for the system interrupt
controller.
4.3.3. Analog To Digital (A/D) Converter (19502.01.02)
The type of Analog to Digital (A/D) Converter that is used in the nanovolt detector is a
charge-balance (integrating) converter. The converter is completely self-running and
performs 50 or 60 22-bit conversions per second. The conversion speed is set by the 50/60
Hz option switch on the nanovolt detector cpu assembly, to get excellent normal mode
rejection at the line frequency. Note that ADC Beta must be increased by 1.2 (60/50) for 50
Hz operation, to agree with the increased integration time. The nanovolt detector selects
the appropriate ADC Beta on power up or reset by reading the option switch to determine if
50 Hz or 60 Hz operation has been selected.
One conversion of the A/D converter consists of two blocks of data. One block of data
comes from the charge-balance clock that is counted during a conversion and the other
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