Section 4
4-31
4.3.4.2. Input And Range Selection.
Control data from the CPU (SD) for Input and Range Selection is clocked into the
shift register U200 by a clock signal (SCLK) provided by the CPU PCB. SCLK is
also monitored by the monostable U201, which provides U200 a signal used to latch
the data after all the data has arrived.
The data in the register of U200 is fed to 2 line to 4 line decoder U202 and U 203.
This is used to drive the comparators U205, U206 and U207 to select the input and
range to be measured. It should be noted that the input FET drive signals have both
pull up resistors and pull down resistors so that the drive for Q103-Q108 and Q115
is -7 V.
Range selection FET signals do not have pull down resistors and so FETs Q100-102
and Q303-305 are driven to -15 V.
4.3.4.3. Charge Pump.
The switching on the input FET Q104 injects or removes small quantities of charge
from the input. U208 provides a signal which is coupled to the input by C201, to
either remove or add a small amount of charge to compensate switching charge
addition or removal respectively.
4.3.4.4. Attenuator.
U106 is a FET input op-amp which buffers the input signal. The signal is then
divided by R118-R120 to provide signals for the 2 V and 20 V ranges.
4.3.4.5. Power Supplies.
U301 and U302, along with their resistor and capacitor networks, regulate the
system ±15 V to ±13 V for use on the Analog Amplifier PCB. U105 with its
network provides a floating ±9 V supply, which is used to power the input
differential pair Q300. The circuitry including Q111-Q114 provides bootstrapped
±8 V supply for the input attenuator buffer U106.
4.3.4.6. Overload Protection.
Input Overload Protection is provided by Q109, Q110, VR100, VR101, R105,
R106, and R117. When the voltage between the input terminals exceeds 25 volts,
Q109 or Q110 is forward biased and starts to conduct. The power is dissipated
through R117.
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