hilscher netX 90 - Default Chapter; Table of Contents

Introduction 2/227
netX 90 | Technical data reference guide
DOC160609TRG02EN | Revision 2 | English | 2018-09 | Preliminary | Public © Hilscher, 2017-2018
Table of contents
1 Introduction ............................................................................................................................................. 5
1.1 About this document ...................................................................................................................... 5
1.2 List of revisions............................................................................................................................... 5
1.3 References to documents .............................................................................................................. 5
2 General description and features ......................................................................................................... 6
2.1 Block diagram................................................................................................................................. 8
2.2 Technical data netX 90 .................................................................................................................. 9
2.3 netX 90 signal description ............................................................................................................ 11
3 Core ....................................................................................................................................................... 16
3.1 CPU .............................................................................................................................................. 16
3.1.1 Cortex®-M4 CPU ............................................................................................................................ 16
3.1.2 xPIC CPU ........................................................................................................................................ 16
3.2 DMAC ........................................................................................................................................... 17
3.2.1 Overview ......................................................................................................................................... 17
3.2.2 Features .......................................................................................................................................... 18
3.2.3 Typical applications ......................................................................................................................... 18
3.2.4 Functional description...................................................................................................................... 19
3.2.5 Data transfer .................................................................................................................................... 20
3.2.6 DMA channel priority ....................................................................................................................... 21
3.2.7 DMA flow control ............................................................................................................................. 21
3.3 Crypto core ................................................................................................................................... 21
3.4 Memory map ................................................................................................................................ 22
3.5 Brown-Out Detector (BOD) .......................................................................................................... 23
3.6 Power-on reset and DC/DC ......................................................................................................... 24
3.7 System clock (oscillator) .............................................................................................................. 25
3.8 Temperature sensor ..................................................................................................................... 25
3.9 Interrupt vectors ........................................................................................................................... 26
3.10 Timer ............................................................................................................................................ 28
3.10.1 CPU timer ........................................................................................................................................ 28
3.10.2 IEEE 1588 system time ................................................................................................................... 29
3.11 Watchdog ..................................................................................................................................... 30
3.11.1 Function ........................................................................................................................................... 30
3.11.2 WDG_ACT signal ............................................................................................................................ 30
3.12 Internal memory ........................................................................................................................... 31
3.12.1 Internal Flash ................................................................................................................................... 31
3.12.2 Internal RAM ................................................................................................................................... 31
3.13 External memory .......................................................................................................................... 32
3.13.1 Overview ......................................................................................................................................... 32
3.13.2 Features .......................................................................................................................................... 33
3.13.3 SDRAM interface ............................................................................................................................. 34
3.13.4 SRAM/Flash interface to memory interface controller ..................................................................... 46
4 Booting and SYS LED .......................................................................................................................... 57
4.1 Boot sequence ............................................................................................................................. 57
4.2 Alternative boot mode .................................................................................................................. 59
4.3 System LED ................................................................................................................................. 59
5 Interfaces ............................................................................................................................................... 60
5.1 MMIO - Multiplex Matrix ............................................................................................................... 60
5.2 Host interface ............................................................................................................................... 62
5.2.1 Overview ......................................................................................................................................... 62
5.2.2 Block diagram .................................................................................................................................. 62
5.2.3 Features .......................................................................................................................................... 63
5.2.4 Dual-port memory interface structure .............................................................................................. 64
5.2.5 Parallel dual-port memory interface ................................................................................................. 65
5.2.6 Serial dual-port memory interface ................................................................................................... 78
5.2.7 Handshake registers........................................................................................................................ 85
5.2.8 Parallel dual-port memory timing ..................................................................................................... 88
5.2.9 Serial dual-port memory timing ...................................................................................................... 118
5.3 SQI/SPI ...................................................................................................................................... 127
5.3.1 Overview ....................................................................................................................................... 127
5.3.2 SQI ................................................................................................................................................ 129