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Hitachi AP1 - Page 108

Hitachi AP1
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HMCS46C,HMCS46CL--------------------------------------------------------
Group
Mnemonic
Function
MNEI i M
~
i
VNEI i V
~
i
ANEM A
~
M
Compare
Instruction
BNEM B
~
M
ALEI i A
:s;::
i
ALEM A
~
M
BLEM B
~
M
RAM Bit
Manipulation
SEM n
"1"
-.
M (n)
REM n
"0"
-.
M (n)
Instruction
TM
n
Test
M (n)
BR a
Branch
on
Status
1
CAL a
Subroutine
Jump
on
Status
1
ROM Address
LPU u
Load Program
Counter
Upper
on
Status
Instruction
TBR p
Table
Branch
RTN
Return
from
Subroutine
SEIE
"1"
-.
I/E
SEIFO
"1"
-.
IFO
SEIFl
"1"
-.
IFl
SETF
"1"
-.
TF
SECF
"1"
-.
CF
REIE
"0"
-.
I/E
REIFO
"0"
-.
IFO
REIFl
"0"
-.
IFl
Interrupt
Instruction
RETF
"0"
-.
TF
RECF
"0"
-+
CF
TIO
Test
INTo
Til
Test
INT,
TIFO
Test
IFO
TlFl
Test
IFl
TTF
Test
TF
LTI i
i
-.
Timer/Counter
LTA
A
-.
Timer/Counter
LAT
Timer/Counter
.....
A
RTNI
Return
Interrupt
"---
SED
~'1"
~
o (V)
RED
"0"
-.
o (V)
TO
Test
o (V)
SEOO
n
"1"
-.
o (n)
Input/Output
REDO n
"0"
-.
o (n)
Instruction
LAR p
R(p)
-+
A
LBR p
R(p) -+
B
LRA
P
A
-.
R (p)
LRB p
B
-.
R (p)
P p
Pattern
Generation
NOP
No
Operation
[NOTE) 1. (XV)
after
a mnemonic code has four meanings
as
follows.
Mnemonic only
Mnemonic with X
Mnemonic with V
Mnemonic with
XV
[Example)
lAM
lAMX
lAMY
lAMXV
Instruction execution only
After instruction execution, X
++
SPX
After instruction
execution,
V ++ SPY
After instruction
execution,
X ++ SPX, V ++ SPY
M A
M
A,
X ++ SPX
M
A,
V ++ SPY
M
A,
X ++ SPX, V ++
Spy
Status
NZ
NZ
NZ
NZ
NB
NB
NB
M(n)
1
1
1
INTo
INT,
IFO
IFl
TF
O(V)
2. Status
column
shows
the
factor which brings
the
Status
F/F
"1"
under judgement instruction
or
instruction accompanying
the
judgement.
NZ
....
AlU
Not Zero
C
.....
AlU
Overflow
in
Addition,
that
is, Carry
NB
....
AlU
Overflow
in
Subtraction,
that
is,
No Borrow
Except above
.......
Contents
of
the
status
column
affects
the
Status
F/F
directly.
3. The Carry
F/F
(C(F/F))
is
not
always affected by executing
the
instruction which affects
the
Status
F/F.
Instructions which affect
the
Carry F/F are eight as follows.
AMC
SEC
SMC
REC
DAA
ROTl
DAS ROTR
4.
All
instructions
except
the
pattern
instruction
(P)
are executed in 1-cycle.
The
pattern
instruction
(P)
is
executed
in
2-cycye.
106