HP 3000 Series - Page 72

A
Apparatus used with Off-board Loopback tests, 1-3, 1-5, 5-12
B
Backplane compatibility, 2-3
Basic Instruction Set Test, 5-4
BI SYNC data communication, 4-3
BISYNC Test, 5-5
Block diagram, !NP, 4-2
Board test hood, 1-3, 1-5, 5-12
c
Cable routing, data communications, 2-13, 5-1
Cable routing, memory power modification, 2-12
Cable test connector, 1-3, 1-5, 5-12
Cables, data communication, installation of, 2-13
Cables, data communication, list of, 1-4
Card cage backplane, 1-2, 2-3
CE-supplied test equipment, 1-3, 1-5
Chip tests, 5-5
CMOS/SOS microprocessor, 4-1
Communication cable routing, 2-13, 5-1
Communication cables, installation of, 2-13
Communication line interfaces, 4-4
Compatibility, backplane, 2-3
Compatibility, test equipment, 1-5
Components on !NP PCAs, location of pertinent, 5-7
Configuration dialogue, C-2
Configuration overview, C-1
Configuring MPE, C-1
Connector, cable test, 1-3, 1-5, 5-12
Contents of this manual, vii
CS/Tr ace, 5-2
D
Data communication cables, installation of, 2-13
Data communication cables, list of, 1-4
Data transfer rate, 1-8
DC POWER switches, location of, 2-8, 2-9
Defective RAM data chips, identifying, 5-10
Description of the INP Self Test, 5-3
Device priorities, 2-5, A-1
Diagnostic/Support Monitor (DSM} , 5-2
Dialogue, configuration, C-2
Direct Memory Access (DMA} , 4-3
DMA, 4-3
DRI' number switches, 2-5
DRT number switches, location of, 2-4, 2-5
Tnrlov-1
INDEX