HP 3245A - Page 25

WORST-CASE TIMING
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DATA SETUP FOR WRITE IS THE SAME SINCE DS- S ETUP IS 311lnS AND MUST AL SO PASS HCI39
DATA SETUP FOR READ IS EASILY ACHIEVED SINCE WE ARE MUCH FASTER THAN RAM/ROM
DAT A HOLD FOR READ IS EASILY ACHIEVED SINCE 6801110 NEEDS 0
DATA HOLD FOR WR IT E IS EASILY ACHIEVED SINCE 68000 HOLDS 30nS BEFORE DS-
DTA CK RELEASE TIME IS EASILY ACHIEVED SINCE 68000 ALLOWS 245nS
TIMING FOR ' CRAM - REGISTERS IS SIMILAR (CRAM- IS GAT ED BY AS- AND D S- IN PAL)
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PART/MATERIAL-DESCRIPTION MAT ' L-PART NO. MAT'L-DWG. NO MAT'L-SPEC.
U4 7(OCOM) 14(+SV)
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RB
3-MAR-89
03245-66502
DRAWN BY DATE
[hpJ
HEWLETT
PACKARD
ENGINEER/CHECKER
DC / AC SOURCE
BACKPLANE
&
INTERFACE
RELEASE
TO PROD. TITLE P ART NUMBER
Cl-REVA
20-AUG-90
I
Ic-
SUPERSEDES DWG. SCALE
SHEET 1
OF 1
03245
- 66502 -
1
Scans by Artekmedia => 2010