HP 3312A Service Manual

Section IV
for
the
low
frequencies
while
the
ac-coupled
high-frequency
path
is
optimized
for
wide
bandwidth.
The
two
paths
are
summed
in
the
final
gain
stage
and
then
buffered
through
cascaded
emitter-followers
to
the
output.
4-12.
The
Output
Attenuator
provides
selectable
attenua-
tion
for
the
output
and
an
impedance
match
to
the
$0
ohm
output
terminal.
The
attenuator
reduces
the
amplitude
of
the
output
signal
by
factors
of
1,
10,
100,
or
1000.
4-13.
FUNCTIONAL
BLOCK
DIAGRAM
DESCRIPTION.
4-14.
Refer
to
the
Functional
Block
diagram,
Figure
7-1
for
the
following
discussion.
Detailed
circuit
descriptions
are
referenced
to
figures
or
to
the
circuit
diagrams
of
Section
VIL
4-15.
The
3312A
can
be
divided
into
three
major
sections:
1.
Main
Generator
Section
(Paragraph
4-16)
2.
Output
Section
(Paragraph
4-29)
3.
Modulation
Section
(Paragraph
4-33)
4-16. Main Generator Section,
4-17.
Tuning
Amplifier.
The
Tuning
Amplifier
is
a
sum-
ming
amplifier
which
sums
any
current
from
the
VCO
INPUT
or
the
modulation
source
with
the
current
present
at
the
input
of
the
amplifier.
The
output
voltage
of
the
amplifier
is
a
weighted
average
of
the
input
signal
voltages.
The
Frequency
Control
(Dial)
varies
the
amount
of
voltage
seen
at
the
output
of
the
Tuning
Amplifier,
which
determines
the
frequency.
4-18.
Symmetry
Switch
and
Vernier.
The
front
panel
Symmetry
Switch
operates
in
two
modes.
With
the
front
panei
control
in
the
CAL
position
(Figure
4-2)
the
output
of
the
Tuning
Amplifier
is
connected,
through
two
nomi-
nal
5
kw
resistors,
to
the
non-inverting
input
of
Ui02
and
the
inverting
input
of
U103.
Because
the
gain
of
U102
is
equal
to
that
of
U103,
the
magnitude
of
the
voltage
at
the
emitters
of
QIO
and
Q102
is
equal,
but
due
to
the
inversion
of
U103,
the
emitter
of
Q101
is
positive
with
* RID + RIZ] = RI24
231288 - 40344
Figure 4-2. Calibrated Symmetry.
4-2
Model 3312A
respect
to
ground
and
the
emitter
of
Q102
is
negative
with
respect
to
ground.
In
the
calibrated
position,
equal
currents
flow
through
R122
and
R123.
4-19.
During
variable
symmetry
operation
(Figure
4-3),
the
output
of
the
Tuning
Amplifier
goes
to
the
wiper
arm
of
the
symmetry
Vernier,
and
the
junction
of
R122
and
R123
is
grounded.
Adjusting
the
position
of
the
wiper
arm
varies
the
input
resistance
of
U102
and
U103
and,
therefore,
the
gain,
The
emitters
of
Q101
and
Q102
will
remain
opposite
in
polarity,
but
the
magnitude
cf
the
voltage
will
differ.
In
addition,
different
currents
will
flow
through
R122
and
R123,
which
means
different
currents
in
the
integrating
capacitance,
so
that
the
output
waveform
will
no
longer
have
a
50%
duty
cycle.
Instead,
the
duty
cycle
may
be
varied
from
80%
to
20%
or
20%
to
80%.
4-20. Positive and Negative Current Sources. The voltages
set up by the symmetry stage are transferred to the
integrating
current
sources
through
two
operational
ampli-
fiers.
Since
amplifier
input
impedance
is
near
infinity,
zero
current flows into the amplifier, consequently the voltage
across
R119
+
R121
and
R124
will
appear
across
R117
and
R126
respectively.
The
collector
diodes
of
Q106
and
Q107
(Figures 7-2) are current sources controlled by the emitter
current
established
by
R117
and
R126.
The
RANGE
Hz
switches change the parallel resistances of R117 and R126
which influence the ramp time of the integrating capaci-
tance and, therefore, the frequency.
4-21.
Diode
Switch.
The
gating
circuit
of
the
Diode
Switch
(Figure
7-2)
allows
for
the
charge
or
discharge
of
the
integrating
capacitance.
The
high
speed
comparator,
U201
(Figure
7-3),
controls
the
signal
path
through
the
switch.
When
pin
2
of
U201
is
high,
CR204
and
CR206
are
conducting,
CR203
and
CR207
are
reverse
biased,
and
the
integrating
capacitor
charges.
When
pin
2
goes
low,
CR203
and
CR207
conduct,
CR204
and
CR206
are
reverse
biased,
and
the
integrating
capacitor
discharges.
% RIO + Ri2gi= Ri24
HUBS Nt NTT FI PAA TTT Pe A AA ll rr Fra
S324 B- 4035
Figure
4-3.
Variable
Symmetry.

HP 3312A Specifications

General

Brand	HP
Model	3312A
Category	Inverter
Language	English