HP 8340b - Page 81

KNOBX in line 60 counts the pulses that occur in the sampling-time interval (the sampling time
range is 0.01-2.55 seconds, but the sampling time must be short enough to keep the pulse count in
the range of —127 to +128), and assigns the value of that count to arbitrary variable Count. Line
70 displays the pulse counts on the computer's CRT (pulse counts of ±1-30 are typical for this
sampling time). Line 80 sends the pulse count information to the HP 8340B/41B, where it affects
the active function (CW in this example).
In line 80, the pulse count is converted from decimal to binary by the CHR$ function, and concate¬
nated to the RB code. One byte of numerical data can accompany RB, so the decimal value of
Count has an allowable range of —127 to +128. The sampling time is arbitrary; 75 milliseconds
was selected for this example because the resultant response of the computer’s knob approxi¬
mates the response from the HP 8340B/41B’s knob (the exact effects of the sampling time must
be ascertained by experiment).
REb, RMb Request mask Extended, and Request Mask, allow masking of the extended status
byte (status byte 2) and the service request status byte (status byte 1), respectively. Masking is
usually done for interrupt programming, where non-critical bits of the status bytes are masked to
prevent them from initiating an unimportant interrupt.
To mask a status byte, the HP 8340B/41B must receive the RE and/or RM code that includes the
numerical value of the enabled bits. The numerical value of the bits, in decimal, is:
BIT 7 6 5 4 3 2 1 0
DECIMAL 128 64 32 16 8 4 2 1
For example, to enable bit 2 on status byte 1 while occluding the six other bits, the programming
code is ”RM”&CHR#(4), where the decimal value of bit 2 is converted to binary by the CHR$
function and concatenated to the RM code.
Masked interrupt programming requires the identification and enabling of the computer’s inter¬
rupt register, and the transmission of the RM/RE codes to the HP 8340B/41B. Here is a typical
BASIC example:
100 OUTPUT 719; "CS"
110 OUTPUT 719; "RM , , & C H R $ ( 4 >
120 OUTPUT 719; "RE"&CHR$(64)
130 ENABLE I NTR 7; 8
140 ON I NTR 7 GOTO 500
150 OUTPUT 719; "PLEK"
500 PRINT "WARNING: RF UNLEVELED"
Line 110 enables bit 2 (only) of status byte 1, which is the bit that causes an SRQ to be sent
when any of the bits in status byte 2 change. Line 120 enables bit 6 (only) of status byte 2,
which detects an unleveled RF output. Thus, an unleveled RF is the only condition that will
cause the HP 8340B/41B to send an SRQ.
Line 130 enables the computer’s interrupt register that is associated with I/O port 7, and
instructs the computer to monitor bit 3 (decimal 8) for a true condition. Bit 3, in this example, is
the SRQ RECEIVED bit, but the actual bit depends upon the particular computer being used
(e.g., bit 2 for the HP 9826A (926), bit 3 for the HP-85A). Line 140 directs the program in the
event of a true bit 3, which could occur if the power level is set too high (line 150 allows
operator adjustment of the power level via the rotary [KNOB]).
Once set, several status byte bits remain latched until cleared by CS or CLEAR (or until after
the status bytes are read a second time). The OS explanation describes all status byte bits.
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Operating Information
HP 8340B/41B