HP Lab Series User Manual

as
the
switching
element.
The
SCR
is
fired
once
during
each
half-cycle
(8.33
milliseconds)
of
the
.
rectified
ac
{see
Figure
4-3).
Notice
that
when
the
SCR
is
fired
at
an
early
point during
the
half-cycle
the
de
level
applied
to
the
series
regulator
is
fairly
high.
When
the
SCR
is
fired
later
during
the
cycle,
the
de
level
is
relatively
low.
"Figure
4-3.
SCR
Phase
Control
Over DC Input Level
4-16
The SCR
control
circuit
samples
the
input
line
voltage,
the.
output
voltage, and
the
voltage
aaoss
the
sertes
transistor.
It
generates
a
firing
pulse,
at
the
time
required,
to
fire
the
SCR
so
that
the
voltage
aaoss
input
capacitor
Cl4
will
be
maintained
at
the
desired
level.
4-17
The
inputs
to
the
co~trol
circuit
are
algebra-
ically
summed
aaoss
capacitor
C22.
All
inputs
contribute
to
the
time
required
to
charge
C22.
The
input
line
voltage
is
rectified
by
CR9
and
CR12,
attenuated
by
voltage
divider
RlOO
and
RlO
1,
and
applied
to
the
summing point
at
TP66
via
capacitor
C22.
Capacitor
C23
is
used
for smoothing
purposes.
Resistor
R82,
connected
between
the
minus
output
terminals
and
the
summing point,
furnishes
a
volt-
age
drop
which
is
proportional
to
the
output
voltage.
Resistors
R91
and
R92
sample
the
voltage
across
the
series
transistor,
Q6. Resistor
R93
and
capaci-
tor
C24
stabilize
the
control
circuit
feedback.
loop.
Resistors
R97
and
R99
are
the source-.of
an
offset
current
which
varies
with
the
output
current.
This
offset
current
sustains
a negative charging
current
to
the
summing
capacitor
ensuring
that
the
SCR
will
fire
at
low
output
voltages.
4-3
TP66
SUMMING
POINT
--r
1.25V
---~
;_
__
_1
_
_l
~8.3MS-j
I
I
j
I
I
f111
1 I I
1---r
TP67
16V
OUTPUT
019
.
__l
ov-
I
I
I
I
:
ll
:
[1---r
TP68(+l/T2
(-l
I I
12V
Fl
RING
PULSE
I
·-·
I .
_i
TP6!5
RESET
NOTES:
ov---,
•
I
Ou
SEC.I
1--
I
I
I
____
_
ov-~
1.
ALL
WAVEFORMS
TAKEN
AT
MAXIMUM
RATED
OUTPUT
VOLTAGE
WITH
NO
LOAD
CONNECTED.
2.
SCOPE
DC
COUPLED
ANO
REFERENCED
TO
INBOARD
SIDE
OF
CURRENT
SAMPLING
RESISTOR
EXCEPT
FOR
FIRING PULSE.
3.
FOR
CLARITY,
WAVEFORMS
ARE
NOT
DRAWN
TO
SCALE.
Figure
4-4.
Preregulator
Control
Circuit
Waveforms
4-18
The summation
of
the
input
signals
results
in
the
generation
of
a
voltage
waveform
similar
tQ
that
shown
on
Fiqure
4-4.
The
linear
ramp portion
of
the
waveform
starts
at
zero
Volts (with no load
connect-
ed
and
at
full
rated output voltage)
and,
when a
certain
negative
threshold
voltage
is
reached,
for-
ward
biases
diodes
CR16
and
CRl
7.
The
negative
voltage
then
is
coupled
to
the·
base
of
transistor
Ql8.
Transistors
Ql8
and
Ql9
form a
squaring
cir-
cuit
similar
to
a
Schmitt
trigger
configuration.
Ql8
is
conducting,
prior
to
firing
time,
due
to
the
posi-
tive
bias
connected
to
its
base
through
R94.
Tran-
sistor
Ql9
is
cutoff
at
this
time
because
its
base
is
connected
directly
to
the
collector
of
conducting
transistor
Ql8.
When
the
negative
threshold
volt-
age
is
reached,
transistor
QlB
is
driven
towards
cutoff
and
transistor
Ql9
begins
to
conduct.
The
collector
voltage
of
Ql9
decays
very rapidly
as
shown
on
Figure
4-4.
The
conduction
of
Ql.9
allows
capacitor
Cl7
to
discharge
rapidly
through
pulse
transformer
T2
resulting
in
the
SCR
firing
pulse
shown
on
the
diagram. The firing
pulse.is
relatively
narrow (about
10jl.Sec)
because
when
Ql9
reaches
saturation
the
magnetic
field
surrounding
T2
col-
lapses
driving
the
voltage
in
a
negative
direction.
4-19
Reset
of
the
control
circuit
occurs
once
every
8 .33
milliseconds
when
the
rectified
ac
voltage
at
TP65
recedes
to
a
level
at
which
diode
CR15
be-
•
•
•

HP Lab Series Specifications

General

Brand	HP
Model	Lab Series
Category	Power Supply
Language	English