Chapter 2. System Board Features
IDE Bus Master Interface
The system board incorporates a PCI-to-IDE interface that complies with the
AT Attachment Interface with
Extensions
. The Intel PIIX4 chipset module contains the controller for the PCI Bus Master IDE interface.
The PIIX4 module allows concurrent operations on the PCI and IDE buses. (Refer to “Chip Set Control”
on page 7 for further information on the PIIX4 module.)
The primary and secondary IDE busses are routed to two connectors on the system board. A total of four
IDE devices can be attached to the two IDE system board connectors using ribbon cables. The IDE
devices receive their power through separate, four-position power cables containing +5 V, +12 V, and
ground (GND) voltage.
On each IDE connector, one IDE device is designated as the primary (master) device, and the other
device is designated as the secondary (subordinate) device. These designations are determined by switch
or jumper settings on each IDE device. A functional primary device must be present on each IDE
connector for a secondary device to be recognized on that same IDE connector. Care must be taken to
ensure that the jumpers on the IDE devices installed in the system correctly identify them as either primary
or secondary devices. Otherwise, some of the devices might not be recognized by the system. There is
no performance impact between a primary device and a secondary device of the same type on the same
IDE connector.
A bootable IDE hard disk drive can be installed on either IDE connector. A bootable hard disk is one
which has an active partition with an operating system installed on it.
PCI or ISA IDE expansion adapters are not supported.
For a list of devices that can be installed in IntelliStation M Pro computers, refer to “Internal Drives” on
page 24.
The following table shows the typical system resource assignments for the IDE interface.
Notes:
1. IDE 1 is the default for the primary channel.
2. IDE 2 is the default for the secondary channel.
When the computer is started, the resource assignments are subject to change during POST.
Two 40-pin connectors are provided on the system board for the IDE interface. For information on
connector pin assignments, see “IDE Connectors” on page 42.
Table 1. System Resource Assignments for the IDE Interface
Configuration ROM RAM I/O Address (Hex) IRQ DMA
IDE 1 None None 01F0-01F7, 03F6, 03F7 bits 6:0 14 None
IDE 2 None None 0170-0177, 0376-0377 15 None
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