IBM Personal System/2 50 - Performance Specifications

Specifications
| The following figure describes the Type 1 system board performance.
* N is the number of transfers in the burst.
Number Cycle
Device of Walts Time (ns)
Microprocessor (10 MHz — 100 ns Clock):
Access to System Board RAM 1 300
Access to System Board ROM 1 300
Access to Channel:
Default Transfer Cycle:
/O Access 1 300
Memory Access 0 200
Synchronous Extended Transfer Cycle 1 300
Refresh Rate 500 (min)
(Typically performed every 15.1 ys)
Bus Master Access to System Board RAM 300 (min)
DMA Controller (10 MHz — 100 ns Clock):
Single Transfer: 300 + I/O Access + Memory Access
Burst Transfers: 300 + (I/O Access + Memory Access)N*
System Board Memory Access 300
Default Transfer Cycle:
I/O Access 300
Memory Access 200
Synchronous Extended Transfer Cycle 300
Figure 1-5. Performance Specifications — Type 1 System Board
Model 50 System Overview — October 1990 1-7