IBM Personal System/2 50 - Arbitration Register, Read Hex0090

Central Arbiter Programming
The central arbitration control point provides access to
programmable options through the Arbitration register, which is
accessed at I/O address hex 0090. The bits are defined differently for
read and write operations, as shown in the following figures.
Bit Definition
7 Enable System Microprocessor Cycle
6 Arbitration Mask
5 Enable Extended Arbitration
4-0 Reserved
Figure 3-2. Arbitration Register, Write to Hex 0090
Bit Definition
7 Enable System Microprocessor Cycle
6 Arbitration Masked by NM!
5 Bus Time-out
4 Reserved
3-0 Value of Arbitration Bus During Previous Grant State
Figure 3-3. Arbitration Register, Read Hex 0090
Bit7 Setting this bit to 1 enables system microprocessor cycles
during arbitration cycles. This bit can be set to 0 if an
arbitrating device requires total control of the channel
bandwidth. This bit is set to 0 by a system reset.
Reading this bit as a 1 indicates system microprocessor
cycles are enabled during arbitration.
Bit 6 Setting this bit to 1 causes the central arbitration control
point to enter the arbitration state. The system
microprocessor controls the channel until this bit is reset
to 0. This bit is set to 0 by a system reset.
Reading this bit as a 1 indicates that an NMI has occurred
and has masked arbitration.
Warning: This bit should be set to 1 only by diagnostic
routines and system error-recovery routines.
Bit 5 Setting this bit to 1 enables extended arbitration. The
minimum arbitration cycle is 300 nanoseconds; this bit
extends that minimum cycle to 600 nanoseconds. This bit
is set to 0 during a system reset.
Reading this bit as a 1 indicates that a bus time-out has
occurred, and resets bit 6 in this register to 0.
Model 50 System Board — October 1990 3-5