IBM Personal System/2 50 - Miscellaneous System Functions; Nonmaskable Interrupt; System Control Port B (Hex 0061)

Miscellaneous
System
Functions
Nonmaskable
interrupt
The
nonmaskable
interrupt
(NMI)
signals
the
system
microprocessor
that
a
parity
error,
a
channel
check,
a
system
channel
time-out,
ora
system
Watchdog
time-out
has
occurred.
The
NMI
stops
all
arbitration
on
the
bus
until
bit
6
of
the
Arbitration
register
(I/O
address
hex
0090)
is
set
to
0.
This
can
result
in
lost
data
or
an
overrun
error
on
some
I/O
devices.
The
NMI
masks
all
other
interrupts
and
the
IRET
instruction
restores
the
interrupt
flag
to
the
State
it
was
in
prior
to
the
interrupt.
A
system
reset
causes
a
reset
of
the
NMI.
Nonmaskable
interrupt
requests
from
system
board
parity
and
channel
check
are
subject
to
mask
control
with
the
NMI
mask
bit
in
the
RT/CMOS
Address
register.
The
Watchdog
Timer
and
system
channel
time-out
are
not
masked
by
this
bit.
(See
“RT/CMOS
RAM
1/O
Operations”
on
page
3-14).
The
power-on
default
of
the
NMI
mask
is
1
(NMI
disabled).
Prior
to
enabling
the
NMI
after
a
power-on
reset,
the
parity
check
and
channel
check
State
are
initialized
by
the
POST.
Warning:
The
operation
following
a
write
to
hex
0070
should
access
port
hex
0071;
otherwise
intermittent
malfunctions
and
unreliable
operation
of
the
RT/CMOS
RAM
can
occur.
System
Control
Port
B
(Hex
0061)
Bit
definitions
for
the
read
and
write
functions
of
this
port
are
shown
in
the
following
figures.
Bit Function
Reset
Timer
0
Output
Latch
(IRQO)
4
Reserved
Enable
Channel
Check
Enable
Parity
Check
Speaker
Data
Enable
Timer
2
Gate
to
Speaker
6
OANwI
AN
Figure
3-23.
System
Control
Port
B
(Write)
3-24
Model
50
System
Board
—
October
1990