IBM Series 1 - Page 23

This subset consists of control busses and tags to support
cycle steal and IPL operations. This subset provides the
means to present cycle steal requests to the processor, to
resolve contention, and to service the cycle steal
transfers. In conjunction with the basic and the interrupt
subsets, the cycle steal/1PL subset supports devices that
cycle steal or DPC devices capable of IPL. The I/O signal
lines in the cycle steal/1PL subset are listed in Figure
2-5.
Figure 2-5 (Part 1 of 2).
ufl,g St~2.Ulf1 Subs~.t.--§.g£!ic~ Q£QJ!J! of Sign~l Line§
Address bus bits 00-15*1
Cycle input indicator
Cycle byte indicator
Status bus
Initiate 1PL *2
IPL *2
<------
<---_._-
<------
------)
------>
<------
Figure 2-5 (Part 2 of 2).
£~cl~ ~1,g~lL!f1 Subset--~Qll g£Q~£ 21 ~1g£~! Li~2
16
1
1
4
1
1
No. of lines
Cycle steal request in
Bur:st return *3
(------
<------
1
1
*1 Address bits 00-15 must have full bidirectional
capability for this subset.
*2 Required only for devices supporting IPL.
Initiate IPL is not required for devices that
only support IPL from a host system.
*3 Required only if burst cycle steal transfers are
suppo~ted by the device.
2-8 GA34-0033
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