IBM Series 1 - Page 24

o
Address Bus Bits 00--15. This is a 16 bit bidirectional bus
------- -~- ~ ------
that is received by all I/O devices. The bus is used on
direct program control (DPe) sequences to select and pass
commands to the I/O devices. On DPC sequences, the address
bus bits 00--15 are logically equal to the contents of bits
0--15 of the first vord of the lDCB. The channel select bit
(IDCB bit 0) on address bus bit 0 can be ignored for device
selection.
The address bus is also used on cycle stealing
sequences to present main storage addresses to the channel
controls. On cycle steal service sequences, address bits
00--15 are driven by the I/O device and correspond to the
storage address bits 00--15 of the data to be transferred.
Address bus bits 00--15 are not used on interrupt
service sequences.
!ddre§§ Bus Bi! 12. This bit is an outbound tag received by
all I/O devices. When active, this tag signals a DPC
sequence to the I/O devices. The receiver for this tag is
always enabled.
Q~1~ ~~§. This is an 18 bit bidirectional bus with 16 bits
of data and 2 parity bits (odd parity by byte). The data
bus transfers data and control intormation: (1) between the
processor and the I/O devices on DPC and interrupt service
sequences and (2) bet.ween cycle stealing <lev ices and main
storage on cycle steal service sequences.
On ~gf write seguences, data bus bits 00--15 are
logically equal to the contents of bits 16--31 (sEcond word)
of the IDCB. If a single byte is to be transferred to the
device, the byte is transferred from bits 24--31 of the
rDCB; bits 16--23 should be zero. DPC write sequences are
specified by address bus bit , (IDCB bit 1) equal to logical
one.
Parity is always maintained for both bytes of the data
bus on DPC write sequences. However, certain relaxations of
the requirement to check parity on both bytes are allowed if
a OPC device is byt.e oriented. A byte~Qriented Qevi£~ is a
OPC device that does not use bits 16--23 of the loeB for any
OPC write or control function as specified by bits 1 through
3 of the IDCB. In this case, the device does not need to
examine or parity check data bus bits 00--07 on nrc write or
control sequences. A device that uses bits 16--23 of the
IDCB for at least one DPe write sequence is not a
byte-oriented device. Note that cycle steaiinq devices
cannot be byte-oriented devices because they implement the
start functions.
On .Q!:£ ££ad .sequ~£~§, data bus bits 00--15 are driven
by the device and correspond to bits 16--31 of the IDCB. If
a single byte is to be transferred from the device, the byte
is transferred on data bus bits 08--15 with data bus bits
00--07 equal to logical zero. DPC read sequences are
Processor I/O Channel 2-9