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IBM Series 1 - Page 25

IBM Series 1
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specified
by
address
bus
bit
1
(IDCa
bit
1)
equal
to
logical
zero.
Parity
must
be
maintained
on
both
bytes
of
the
data
bus
on
ope
read
sequences.
Qn
in1~!:.Y.E1
2g£vi~
§.eguences,
the
data
bus
is
used
to
pass
the
interrupt
ID
word
to
the
processor.
Data
bus
bits
00--15
are
driven
by
the
device
and
correspond
to
bits
0--15
of
the
interrupt
10
word.
The
first
byte
of
the
interrupt
10
word
(bits
0--7)
is
the
interrupt
information
byte;
the
second
byte
(bits
8--15)
is
the
device
address
of
the
device
being
serviced.
Parity
must
be
maintained
on
both
bytes
of
the
data
bus
on
interrupt
service
sequences.
On
<,;:Y£l~
2!~~1
§~vi£~
§ggl!~fg§,
the
data
bus
bits
have
the
following
meanings:
1.
Ou!£~!,
~Q£g
!£gQ§!g£--data
bus
bits
00--15
are
logically
equal
to
the
contents
of
the
word
at
the
storage
address
presented
by
the
device.
This
storage
address
must
be
even.
The
device
indicates
an
output
word
transfer
.by
presenting
the
.£:l£1,g
i!!£ut
!.!!.dic,2..!,Q,£
equal
to
logical
0
and
the
£Y£l~
1!y1g
indi2i2£
equal
to
logical
O.
2.
InEY!,
~ord
i£an§ig£--data
bus
bits
00--15
are
driven
by
the
device
and
correspond
to
the
word
at
the
storage
address
presented
by
the
device.
The
storage
address
must
be
even.
The
device
indicates
an
input
word
transfer
by
presenting
the
£.Y.£l~
in.£!!l
inQ.i£~.tQ!:
equal
to
logical
1
and
the
£.I'£!~
hytg
indicator
equal
to
logical
o.
3.
QQ!EY!,
Qyte
·tran2!~£--the
main
storage
address
presented
by
the
dev~ce
determines
the
alignment
of
the
byte
on
the
data
bus.
If
the
storage
address
is
even,
data
bus
bits
00--07
are
logically
equal
to
the
contents
of
the
byte
at
the
storage
address.
If
the
storage
address
is
odd,
data
bus
bits
08--15
are
logically
equal
to
the
contents
of
the
byte
at
the
storage
address.
The
device
indicates
an
output
byte
transfer
by
presenti.ng
the
£1..£1~
in£.!!1
i!!Qlg12£
equal
to
logical
0
and
the
£Y£1g
~.Yl~
i~~1~1Q£
equal
to
logical
1.
4.
rn.El!!,
Qy.!,g
transf~£--the
device
must
align
the
byte
on
the
data
bus
according
to
storage
address
being
presented.
If
the
storage
address
is
even,
data
bus
bits
00--07
are
driven
by
the
device
and
correspond
to
the
byte
at
the
storage
address.
If
the
storage
address
is
odd,
data
bus
bits
08--15
are
driven
by
the
device
and
correspond
to
the
byte
at
the
storage
address.
The
device
indicates
an
input
by
presenting
the
.£.Y.£1~
inpu,!
indic~lQ£
equal
to
logical
1
and
the
£.Y£lg
Qy!g
.!llQicalQ.£egual
to
logical
1.
The
I/O
architecture
allows
both
byte
and
word
cycle
steal
data
transfers
during
the
execution
of
a
given
cycle
2-10
GA34-0033
( \
\.
;
(:

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