IBM Series 1 - Page 26

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steal operation. For example, an operation transferring an
even number of bytes into a data table on an odd storage
boundary could transfer 1 byte, then a number of words, and
then end with a byte transfer.
Parity is maintained on both bytes of the data bus
during cycle steal output transfers. I/O devices must check
both bytes of the data bus regardless whether a word or byte
is being transferred. Parity must be maintained on both
bytes of the data bus on cycle steal input transfers.
Addr~~§ §at~. This is an outbound tag used during DPC
sequences. This tag signals a device that it can respond to
initial selection and begin execution of the command
specified by bits 0--7 of the address bus.
Addr~§§ Gat~ Return. This is an inbound tag used by the
selected device during a DPC sequence. This tag signals:
(1) the reception of address gate, (2) the activation of the
condition code in bus, and (3) the activation of the data
bus for a read sequence.
~~!:.!ic~ Ga!.~. This outbound tag signals the device -that
last captured a poll that a cycle steal or interrupt service
sequence can begin. The I/O device detects the leading edge
of this tag following a poll capture to begin the sequence;
this is called service 9at~ caEt~£e.
service Qat~ Retu£n. This is an inbound tag used by a
device to signal a service gate capture and activation of
the address bus (on a cycle steal sequence), data bus,
condition code in bus. and other tags as required by the
particular cycle steal or interrupt service sequence.
Condition Code In ~y~. This is a 3-bit binary encoded
inbound bus used by the I/O device on DPC, interrupt, and
cycle steal sequences.
On DPC and interrupt service sequences, the condition
code in bus corresponds to the condition code indicators in
the level status register (LSR) as follows:
Condi!ion code in bit
o
1
2
LS"R indicator
Even
Carry
Overflow
Processor I/O Channel 2-11