IBM System/360 Operating Guide

2. With the Address Compare switch set to ROAR
Restart or ROAR Restart Storage Bypass position,
the circuitry registers (not general-purpose,
floating-point, or UCWs) are reset, the ROS
address register is set as specified by switches
F, G, H, and J, and the resulting microprogram
is initiated (with or without affecting main
storage, depending on the setting of the Address
Compare sWitch).
3. \Vith the Address Compare switch set to ROAR
Restart Without Reset, operation is identical to
that of ROAR Restart except that no reset is
initiated.
4. With the Address Compare switch set to any other
position, the address specified by switches F, G,
H,
and J is placed in the instruction counter and
an I-cycle is started.
Address Compare Switch
This switch determines whether the CPU match
circuit is connected to the Read-Only Storage
Address Register (ROAR) or to the Main-Storage
Address Register (SAR) , and the system! s reaction
when an address match occurs. \Vhen the switch
is in any position that contains the term ROAR, the
read-only storage address register is compared to
switches A, B, C, and D; other positions apply to
the main-storage address register. The switch
positions and the associated system responses are
as follows:
Process Position
This position is used for normal problem-program
processing.
ROAR SYNC Position
This position provides a sync pulse (for Field
Engineering purposes) when the address specified
by switches A, B, C, and D matches the contents
of the read-only storage address register (WX
register) .
ROAR Stop Position
With this setting, system operation proceeds until
the contents of the ROAR match the address speci-
fied by switches A, B, C, and D. When this match
occurs, the CPU clock is turned off (at the end of
the ROS cycle in progress) and the system stops.
Early ROAR Stop Position
With this setting, processing proceeds until the
contents of the ROAR match the address specified
by switches A, B, C, and D. When the match occurs,
the CPU clock is turned off (at the end of the current
ROS cycle) and the system stops. The ROAR indi-
cators display the address of the ROS word just prior
to the ROS word-address set in switches A, B, C,
and D. The ROS word djsplayed, however, is the
one at the address specified in switches A, B, C,
and D.
ROAR Restart
ROAR Restart Without Reset, and
ROAR Restart Storage Bypass Positions
These three settings are similar in that the occurrence
of a match between a ROAR address and switches A,
B, C, and D causes the ROAR to be reset to the value
specified by switches F, G, H, and J. In no case
are the general-purpose or floating-point registers,
or the UCW flag bytes reset.
For ROAR Restart, CPU registers are reset
before the ROAR is reset.
For ROAR Restart Storage Bypass, the function
is identical except that main storage is not permitted
to operate; hence, normal problem-program proc-
essing cannot be done in this mode.
In the ROAR Restart without Reset position, the
function is the same as with ROAR Restart except
that no reset is performed.
SAR Restart Position
When a match occurs in this mode, a fixed address
is forced into the ROAR. The basic micro-diagnostic
and clear-UCW routines are performed, the address
specified by switches F, G, H, and J is loaded into
the instruction counter, and an instruction cycle is
started.
SAR Stop Position
When a match between the SAR and switches A, B,
C, and D occurs in this mode, the CPU clock is
stopped at the end of the write cycle in which the
match occurs.
SAR Delayed Stop Position
In this mode, a match between the SAR and switches
A, B, C, and D causes the CPU clock to stop at the
11

IBM System/360 Specifications

General

Brand	IBM
Model	System/360
Category	Desktop
Language	English