Intel 80386

LOCAL BUS CONTROL PAL DESCRIPTIONS
!DEN :=
«LOCALSTATE==WAITING) & OFF)
#«LCCALSTATE==SAMPLECS) & OFF)
#«LOCALSTATE==CMDDELAY) & OFF)
# «LOCALSTATE==IO) & ON) "activate DEN while in 10
# «LCCALSTATE==ENDIO) & ON) "activate DEN while in 10
# ( (LOCALSTATE==MEMORY) & ON) "activate DEN while in lWS access
# «LCCALSTATE==FLOAT) & (!MWTC # ! IOWC)) "remain active 1 CLK2 if write
# «LOCALSTATE==NOTLCCAL) & ( (!ALE & ! CSOWS) "activate DEN if OWS access
# !DEN) "if active ••. remain active
& (RDY # !CLK)); " ••• until last CLK2 of OWS access
!RDY :=
«LOCALSTATE==WAITING) & OFF)
#«LOCALSTATE==SAMPLECS) & OFF)
# «LOCALSTATE==CMDDELAY) & OFF)
# «LOCALSTATE==IO) & OFF)
#«LOCALSTATE==ENDIO) & ON)
"activate RDY at end of 10
#«LOCALSTATE==MEMORY) & «RDY & IDEN & CLK) # (IRDY & ICLK)))
"activate RDY at end of lWS access
#«LCCALSTATE==FLOAT) & OFF)
#«LCCALSTATE==NOTLOCAL) & ( ( RDY &
CLK & ( (!MRDC # ! IORC # ! INTA)
# (!RDY &
# « !MWTC # ! IOWC) & ! DEN)))
!CLK))) ;
"activate RDY at end of OWS access
111111111111111111111111111111111111111111'1111111"111"'1'11111""1111111111111111111111111111111111111111'11111111"111111111"111111111111111111"1111111
test_vectors
( [CLK2, CLK, LOCALS TATE , MIO, DC, WR, CSOWS] ->
[MRDC, MWTC, IORC, IOWC, INTA, ALE, DEN, RDY] )
"[inputs] -> [outputS]
"C C M D W
"L L I C R
"K K LCCALSTATE 0
"2
[c,L,
[c,H,
[c,L,
[c,H,
[e,L,
[c,H,
[c,L,
[c,H,
[c,L,
[c,H,
[c,L,
[c,H,
[e,L,
[c,H,
[c,L,
[c,H,
[c,L,
[c,H,
[c,L,
[c,H,
[e,L,
[c,H,
[c,L,
x , x,x,x,
X I x,X/x,
X I x,x/x,
X , x,x,x,
x , x,x,x,
x , x,x>,x,
X I X,X,X,
X ,x,x/x,
WAITING, x,x,x,
WAITING, x,x,x,
WAITING, x,x,x,
WAITING, x,x,x,
SAMPLECS, H,L,L,
NOTLOCAL, x,x,x,
NOTLCCAL, x,x,x,
NOTLOCAL, x,x,x,
SAMPLECS, H,H,L,
NOTLOCAL, x,x,x,
NOTLCCAL, x,x,x,
NOTLOCAL, x,x,x,
SAMPLECS, H,H,H,
NOTLOCAL, x,x,x,
NOTLOCAL, x,x,x,
C
S
o
W
S
x] ->
x] ->
x] ->
x] ->
x] ->
x] ->
x] ->
x] ->
x] ->
x] ->
x] ->
x] ->
L] ->
L] ->
x] ->
x] ->
L] ->
L] ->
x] ->
x] ->
L] ->
L] ->
x] ->
M M I I I
R
WOO N
D
TRW T
C C C C A
A D R
LED
E N Y
[X,X,X,X,X, X,X,x];"initialize to IDLE and WAITING
[X,X/X,X,X, X/X,X]i
[X,X/X/X,X, x/x,x];
[X/X,X/X/X, X/X,X];
[X/X/X/X/X, x/x,x];
[X/X/X/X/X, x/x,x];
[x,x,x,x,x, x,x/x];
[x/x,x/x,x, x,x/x];
[H,H,H,H,H, H,H,H];
[H,H,H,H,H, H,H,H];
[H,H,H,H,H, H,H,H];
[H,H,H,H,H, H,H,H];"lOOnS SRAM read
[L,H,H,H,H, L,H,H];
[L,H,H,H,H, L,L,L];
[L,H,H,H,H, L,L,L];
[H,H,H,H,H, H,H,H];"lOOnS SRAM read
[L,H,H,H,H, L,H,H];
[L,H,H,H,H, L,L,L];
[L,H,H,H,H, L,L,L];
[H,H,H,H,H, H,H,H];"lOOnS SRAM write
[H,L,H,H,H, L,H,H];
[H,L,H,H,H, L,L,H];
[H,L,H,H,H, L,L,H];
Figure A-2. PAL-2 State Listings (Cont'd.)
A-11