Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU User Manual

R
Intel
®
925X/925XE Express
Chipset
Datasheet
For the Intel
®
82925X/82925XE Memory Controller Hub (MCH)
November 2004
Document Number: 301464-003

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specifications

General

Brand	Intel
Model	925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU
Category	Computer Hardware
Language	English

Summary

Introduction

System Memory Interface

Explains the DDR2 memory controller, channels, bandwidth, and supported technologies.

Signal Description

Host Interface Signals

DDR2 DRAM Channel A Interface

Details the signals associated with the DDR2 memory interface for Channel A.

DDR2 DRAM Channel B Interface

Details the signals associated with the DDR2 memory interface for Channel B.

PCI Express x16 Graphics Port Signals

Describes the signals for the PCI Express x16 graphics port, including differential pairs.

Host Bridge/DRAM Controller Registers (D0:F0)

Device 0 Function 0 PCI Configuration Register Details

Provides detailed descriptions of PCI configuration registers for Device 0, Function 0.

DRAM Error Handling Registers

Registers for DRAM error address, syndrome, and destination reporting (82925X only).

Programmable Attribute Map Registers

System Management RAM Control Registers

MCHBAR Registers

MCHBAR Register Details

Details registers offset from the MCHBAR base address, controlling memory configuration.

Channel A DRAM Rank Boundary Addresses

Channel A DRAM Timing and Control Registers

Defines timing parameters and controller modes for Channel A DRAM.

Channel B DRAM Registers

Defines rank boundary addresses, attributes, timing, and controller modes for Channel B.

DMIBAR Registers—Direct Media Interface (DMI) RCRB

Direct Media Interface (DMI) RCRB Register Details

Details the RCRB registers for the MCH-Intel ICH6 serial interconnect.

DMI VC Resource Control and Status

Host-PCI Express Graphics Bridge Registers (D1:F0)

Device 1 Configuration Register Details

Provides detailed descriptions of PCI configuration registers for Device 1, the PCI Express Bridge.

PCI Command and Status Registers

Bus Numbering and Address Mapping Registers

Link and Slot Capabilities/Control

Power Management Capabilities and Control

System Address Map

Main Memory Address Range (1 MB to TOLUD)

PCI Memory Address Range (TOLUD – 4 GB)

System Management Mode (SMM)

Describes System Management RAM (SMM RAM) usage and MCH support for SMM modes.

Functional Description

Host Interface

System Memory Controller

Describes the MCH's DDR2 memory interface and its capabilities.

System Memory Configuration Register Overview

Provides a brief description of configuration registers controlling system memory operation.

PCI Express

Provides an overview of the PCI Express architecture and its layers.

Power Management