Signal Description
R
Intel
®
82925X/82925XE MCH Datasheet 27
2.3 DDR2 DRAM Channel B Interface
Signal Name Type Description
SCLK_B[5:0] O
SSTL-1.8
SDRAM Differential Clock: (3 per DIMM) SCLK_Bx and its complement
SCLK_Bx# signal make a differential clock pair output. The crossing of
the positive edge of SCLK_Bx and the negative edge of its complement
SCLK_Bx# are used to sample the command and control signals on the
SDRAM.
SCLK_B[5:0]# O
SSTL-1.8
SDRAM Complementary Differential Clock: (3 per DIMM) These are
the complementary differential DDR2 clock signals.
SCS_B[3:0]# O
SSTL-1.8
Chip Select: (1 per Rank) These signals select particular SDRAM
components during the active state. There is one chip select for each
SDRAM rank
SMA_B[13:0] O
SSTL-1.8
Memory Address: These signals are used to provide the multiplexed
row and column address to the SDRAM
SBS_B[2:0] O
SSTL-1.8
Bank Select: These signals define which banks are selected within
each SDRAM rank
DDR2: 1-Gb technology is 8 banks.
SRAS_B# O
SSTL-1.8
Row Address Strobe: This signal is used with SCAS_B# and SWE_B#
(along with SCS_B#) to define the SDRAM commands
SCAS_B# O
SSTL-1.8
Column Address Strobe: This signal is used with SRAS_B# and
SWE_B# (along with SCS_B#) to define the SDRAM commands.
SWE_B# O
SSTL-1.8
Write Enable: This signal is used with SCAS_B# and SRAS_B# (along
with SCS_B#) to define the SDRAM commands.
SDQ_B[63:0] I/O
SSTL-1.8
2x
Data Lines: SDQ_Bx signals interface to the SDRAM data bus
SDM_B[7:0] O
SSTL-1.8
2x
Data Mask: When activated during writes, the corresponding data
groups in the SDRAM are masked. There is one SDM_Bx signal for
every data byte lane.
SCB_B[7:0]
(Intel
®
82925X
Only)
I/O
SSTL-1.8
2X
ECC Check Byte: These signals require a 6-layer board to be routed.
SDQS_B[8:0]
(82925X MCH)
SDQS_B[7:0]
(82925XE MCH)
I/O
SSTL-1.8
2x
Data Strobes: For DDR2, SDQS_Bx and its complement SDQS_Bx#
make up a differential strobe pair. The data is captured at the crossing
point of SDQS_Bx and its complement SDQS_Bx# during read and write
transactions.
SDQS_B[8:0]#
(82925X MCH)
SDQS_B[7:0]#
(82925XE MCH)
I/O
SSTL-1.8
2x
Data Strobe Complements: These signals are the complementary
DDR2 strobe signals.
SCKE_B[3:0] O
SSTL-1.8
Clock Enable: (1 per Rank) SCKE_B is used to initialize the SDRAMs
during power-up, to power-down SDRAM ranks, and to place all SDRAM
ranks into and out of self-refresh during Suspend-to-RAM.
SODT_B[3:0] O
SSTL-1.8
On Die Termination: Active On-die Termination Control signals for
DDR2 devices.
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