Host Bridge/DRAM Controller Registers (D0:F0)
R
70 Intel
®
82925X/82925XE MCH Datasheet
4.1.28 TOLUD—Top of Low Usable DRAM (D0:F0)
PCI Device: 0
Address Offset: 9Ch
Default Value: 08h
Access: R/W
Size: 8 bits
This 8-bit register defines the Top of Low Usable DRAM. TSEG and Graphics Stolen Memory
are within the DRAM space defined.
Bit Access &
Default
Description
7:3 R/W
01h
Top of Low Usable DRAM (TOLUD): This register contains bits 31 to 27 of an
address one byte above the maximum DRAM memory that is usable by the
operating system. Address bits 31 down to 27 programmed to 01h implies a
minimum memory size of 128 MBs.
Configuration software must set this value to the smaller of the following 2 choices:
• Maximum amount memory in the system plus one byte or the minimum address
allocated for PCI memory.
Address bits 26:0 are assumed to be 000_0000h for the purposes of address
comparison. The host interface positively decodes an address towards DRAM if the
incoming address is less than the value programmed in this register.
If this register is set to 0000 0b, it implies 128 MBs of system memory.
2:0 Reserved
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