Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU User Manual

DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
Intel
®
82925X/82925XE MCH Datasheet 105
7.1.9 DMIVC1RCTL1—DMI VC1 Resource Control
MMIO Range: DMIBAR
Address Offset: 020h
Default Value: 00100000h
Access: R/W, RO
Size: 32 bits
This register controls the resources associated with Virtual Channel 1.
Bit Access &
Default
Description
31 R/W
0b
Virtual Channel Enable (EN):
0 = Disable.
1 = Enable.
30:27 RO
0h
Reserved
26:24 R/W
001b
Virtual Channel Identifier (ID): This field indicates the ID to use for this virtual
channel.
23:20 Reserved
19:17 R/W
0h
Port Arbitration Select (PAS): This field indicates which port table is being
programmed. The only permissible value of this field is 4h for the time-based
WRR entries.
16 RO
0b
Load Port Arbitration Table (LAT): When set, the port arbitration table is loaded
based upon the PAS field in this register. This bit always returns 0 when read.
15:8 Reserved
7:1 R/W
00h
Transaction Class / Virtual Channel Map (TVM): This field indicates which
transaction classes are mapped to this virtual channel. When a bit is set, this
transaction class is mapped to the virtual channel.
0 Reserved

Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU Specifications

General

Brand	Intel
Model	925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU
Category	Computer Hardware
Language	English