DMIBAR Registers—Direct Media Interface (DMI) RCRB
R
106 Intel
®
82925X/82925XE MCH Datasheet
7.1.10 DMIVC1RSTS—DMI VC1 Resource Status
MMIO Range: DMIBAR
Address Offset: 026h
Default Value: 0000h
Access: RO
Size: 16 bits
This register reports the Virtual Channel specific status.
Bit Access &
Default
Description
15:2 Reserved
1 RO
0b
VC Negotiation Pending (NP):
0 = Virtual channel is Not being negotiated with ingress ports.
1 = Virtual channel is still being negotiated with ingress ports.
0 RO
0b
Port Arbitration Tables Status (ATS): This bit indicates the coherency status of
the port arbitration table.
1 = LAT (offset 000Ch:bit 0) is written with value 1 and PAS (offset
0014h:bits19:17) has value of 4h.
0 = This bit is cleared after the table has been updated.
7.1.11 DMILCAP—DMI Link Capabilities
MMIO Range: DMIBAR
Address Offset: 084h
Default Value: 00012C41h
Access: R/WO, RO
Size: 32 bits
This register indicates DMI specific capabilities.
Bit Access &
Default
Description
31:18 Reserved
17:15 R/WO
010b
L1 Exit Latency (EL1). L1 not supported on DMI.
14:12 R/WO
010b
L0s Exit Latency (EL0): This field indicates that exit latency is 128 ns to less
than 256 ns.
11:10 RO
11b
Active State Link PM Support (APMS): This field indicates that L0s is supported
on DMI.
9:4 RO
4h
Maximum Link Width (MLW): This field indicates the maximum link width is
4 ports.
3:0 RO
1h
Maximum Link Speed (MLS): This field indicates the link speed is 2.5 Gb/s.