Intel 925 - Pentium D 925 3.0GHz 800MHz 4MB-Cache Socket 775 CPU

MCHBAR Registers
R
Intel
®
82925X/82925XE MCH Datasheet 79
5 MCHBAR Registers
These registers are offset from the MCHBAR base address.
Address
Offset
Register
Symbol
Register Name
Default
Value
Access
100h C0DRB0 Channel A DRAM Rank Boundary Address 0 00h R/W
101h C0DRB1 Channel A DRAM Rank Boundary Address 1 00h R/W
102h C0DRB2 Channel A DRAM Rank Boundary Address 2 00h R/W
103h C0DRB3 Channel A DRAM Rank Boundary Address 3 00h R/W
104–107h — Reserved — —
108h C0DRA0 Channel A DRAM Rank 0,1 Attribute 00h R/W
109h C0DRA2 Channel A DRAM Rank 2,3 Attribute 00h R/W
10A–10Bh — Reserved — —
10Ch C0DCLKDIS Channel A DRAM Clock Disable 00h R/W
10Dh — Reserved — —
10E–10F C0BNKARC Channel A DRAM Bank Architecture 0000h R/W
110–113h — Reserved — —
114–117h C0DRT1 Channel A DRAM Timing Register 900122h R/W
118–11Fh — Reserved — —
120–123h C0DRC0 Channel A DRAM Controller Mode 0 00000000h R/W, RO
124–17Fh — Reserved — —
180h C1DRB0 Channel B DRAM Rank Boundary Address 0 00h R/W
181h C1DRB1 Channel B DRAM Rank Boundary Address 1 00h R/W
182h C1DRB2 Channel B DRAM Rank Boundary Address 2 00h R/W
183h C1DRB3 Channel B DRAM Rank Boundary Address 3 00h R/W
184–187h — Reserved — —
188h C1DRA0 Channel B DRAM Rank 0,1 Attribute 00h R/W
189h C1DRA2 Channel B DRAM Rank 2,3 Attribute 00h R/W
18A–18Bh — Reserved — —
18Ch C1DCLKDIS Channel B DRAM Clock Disable 00h R/W
18Dh — Reserved — —
18E–18Fh C1BNKARC Channel B Bank Architecture 0000h R/W
190–193h — Reserved — —
194h C1DRT1 Channel B DRAM Timing Register 1 900122h R/W, RO