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General| Product Line | Intel Core i5 |
|---|---|
| Model Number | BX80623I52500K |
| Code Name | Sandy Bridge |
| Vertical Segment | Desktop |
| Processor Number | i5-2500K |
| Lithography | 32 nm |
| Base Clock Speed | 3.30 GHz |
| Max Turbo Frequency | 3.70 GHz |
| Cache | 6 MB Intel Smart Cache |
| Bus Speed | 5 GT/s DMI |
| TDP | 95 W |
| Socket | LGA1155 |
| Sockets Supported | LGA1155 |
| Max Memory Size | 32 GB |
| Memory Types | DDR3 1066/1333 |
| Max # of Memory Channels | 2 |
| Max Memory Bandwidth | 21 GB/s |
| ECC Memory Supported | No |
| Integrated Graphics | Intel HD Graphics 3000 |
| Graphics Base Frequency | 850 MHz |
| Graphics Max Dynamic Frequency | 1.1 GHz |
| Intel® Quick Sync Video | Yes |
| Intel® InTru™ 3D Technology | Yes |
| Intel® Flexible Display Interface (Intel® FDI) | Yes |
| Intel® Clear Video HD Technology | Yes |
| # of Displays Supported | 2 |
| PCI Express Revision | 2.0 |
| Max # of PCI Express Lanes | 16 |
| CPU Cores | 4 |
| Threads | 4 |
| Instruction Set | 64-bit |
| Instruction Set Extensions | SSE4.1/4.2, AVX |
| Idle States | Yes |
| Enhanced Intel SpeedStep® Technology | Yes |
| Intel® Demand Based Switching | No |
| Thermal Monitoring Technologies | Yes |
| Intel® Fast Memory Access | Yes |
| Intel® Flex Memory Access | Yes |
| Intel® Identity Protection Technology | Yes |
| Intel® AES New Instructions | Yes |
| Intel® Trusted Execution Technology | No |
| Execute Disable Bit | Yes |
| Manufacturing Process | 32 nm |
| Product Collection | 2nd Generation Intel Core i5 Processors |
| PCI Express Configurations | 1x16 |
Lists documents referenced in this update.
Lists other relevant documents for further information.
Explains notations and codes used in the summary tables.
Defines codes related to processor stepping in summary tables.
Defines codes related to the status of errata in summary tables.
Addresses failure of I/O restart in SMM after MCE, leading to potential system halt.
Details invalid MCA register data due to reset conditions and PWRGOOD signal.
Explains data corruption from aliased UC code and WB data in cache lines.
Describes locked transactions not being retried when BINIT# is asserted.
Clarifies the definition and usage of the Time Stamp Counter (TSC).
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