Host Bridge/DRAM Controller Registers (D0:F0)
R
Intel
®
82925X/82925XE MCH Datasheet 53
4.1.10 SID—Subsystem Identification (D0:F0)
PCI Device: 0
Address Offset: 2Eh
Default Value: 0000h
Access: R/W/O
Size: 16 bits
This value is used to identify a particular subsystem.
Bit Access &
Default
Description
15:0 R/WO
0000h
Subsystem ID (SUBID): This field should be programmed during BIOS
initialization. After it has been written once, it becomes read only.
4.1.11 CAPPTR—Capabilities Pointer (D0:F0)
PCI Device: 0
Address Offset: 34h
Default Value: E0h
Access: RO
Size: 8 bits
The CAPPTR provides the offset that is the pointer to the location of the first device capability in
the capability list.
Bit Access &
Default
Description
7:0 RO
E0h
Pointer to the offset of the first capability ID register block: In this case the
first capability is the product-specific Capability Identifier (CAPID0).