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General| Architecture | x86 |
|---|---|
| Core Count | 1 |
| Microarchitecture | NetBurst |
| Manufacturer | Intel |
| Core Names | Willamette, Northwood, Prescott, Cedar Mill |
| Virtualization Technology | No |
| Release Date | November 20, 2000 |
| Clock Speed | 1.3 GHz to 3.8 GHz |
| FSB Speed | 400 MHz to 1066 MHz |
| Socket | Socket 423, Socket 478, LGA 775 |
| Introduced | 2000 |
| Product Line | Pentium |
| Front Side Bus | 400 MHz to 1066 MHz |
| Hyper-Threading | Yes (Prescott and later) |
| 64-bit Support | Yes (Prescott and later) |
| Instruction Set | MMX, SSE, SSE2, SSE3 |
| Discontinued | 2008 |
| Process Technology | 180 nm, 130 nm, 90 nm, 65 nm |
| L2 Cache | 256 KB, 512 KB, 1 MB, 2 MB |
| Lithography | 180 nm, 130 nm, 90 nm, 65 nm |
| L1 Cache | 8 KB |
Guidelines for routing system bus clocks, including BCLK topology.
Defines critical RDRAM device clock routing lengths.
Specifies termination requirements for RDRAM device clocks.
Details topology and routing recommendations for system bus signals.
High-speed RSL signals transmit data between MCH and RDRAM.
Calculations for clock trace length for microstrip and stripline routing.
Termination requirements for RSL signals to 1.8 V (Vterm).
Recommended routing guidelines for Intel 850 chipset AGP interface.
Line length and mismatch requirements for 2X/4X AGP signals.
Routing guidelines for AGP interfaces less than 6 inches.
Routing guidelines for AGP interfaces over 6 inches.
Recommendations for processor voltage regulator and decoupling capacitors.
Example placement for FMB1 VR components.
Decoupling requirements for FMB1 processor power delivery.
Illustrates power delivery shapes for FMB1 on a 6-layer board.
Checklist for all processor signals' recommendations and reasons.
Checklist for Intel 850 Chipset recommendations and their impact.
Checklist for Intel ICH2 interface recommendations.
Layout considerations for processor and system bus signals.
Recommendations for AGTL+ signal layout and trace width.
Layout for asynchronous GTL+ and other signals.
Placement guidelines for processor decoupling capacitors.
Decoupling recommendations for the Intel 82850 MCH.
Routing recommendations for Rambus Signaling Level (RSL) signals.
Routing guidelines for 2X/4X AGP signals.
AGP routing trace length and spacing for interfaces < 6 inches.
AGP routing trace length and spacing for interfaces > 6 inches.
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