Intel Pentium 4 User Manual

Memory Interface Routing
R
90 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
6.1 Rambus RDRAM* Device Routing Guidelines
The MCH has two Direct Rambus channels. The layout guidelines presented below are applicable
for each channel. One channel should be routed entirely microstrip (outer layers) or stripline (inner
layers). Figure 56 illustrates an example routing topology for the MCH.
Figure 56. Intel
®
MCH Direct Rambus Channel Routing Example
RDRAM-CH_Route
MCH
RAC B
VTERM
RIMM
Connector
MCH
RAC A
VTERM
RIMM
Connector
Board Stackup
Channel A
Signal
Power
Channel B Signal
Channel B
Signal
Ground
Channel A Signal
The signals on the Direct Rambus channel are broken into three groups: Rambus Signaling Level
(RSL) signals, CMOS signals and clocking signals. The signal groups are documented in Table 21.

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB