Intel Pentium 4 User Manual

AGP Interface Routing
R
120 Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide
The MCH G_PAR signal also needs an external pull-up resistor. This signal must have an external
pull-up resistor to ensure that G_PAR remains at a valid logic level during AGP protocol
transactions.
Table 27. AGP Pull-up/Pull-down Resistors
Signals PU/PD Requirement
1x Timing Domain
FRAME# pull-up resistor to VDDQ
TRDY# pull-up resistor to VDDQ
IRDY# pull-up resistor to VDDQ
DEVSEL# pull-up resistor to VDDQ
STOP# pull-up resistor to VDDQ
SERR# pull-up resistor to VDDQ
PERR# pull-up resistor to VDDQ
RBF# pull-up resistor to VDDQ
PIPE# pull-up resistor to VDDQ
REQ# pull-up resistor to VDDQ
GNT# Pull-up resistor to VDDQ
WBF# pull-up resistor to VDDQ
PAR# Pull-up resistor to VDDQ
INTA# pull-up resistor to 3.3 V
INTB# pull-up resistor to 3.3 V
2x/4x Timing Domain
AD_STB[1:0] pull-up resistor to VDDQ
SB_STB pull-up resistor to VDDQ
AD_STB[1:0]# pull-down resistor to GND
SB_STB# pull-down resistor to GND

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB