I/O Controller Hub 2
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162 Intel
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Pentium
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4 Processor / Intel
®
850 Chipset Family Platform Design Guide
9.8.9 Power Supply PS_ON Consideration
• If a pulse on SLP_S3# or SLP_S5# is short enough (~ 10–100 ms) such that PS_ON is driven
active during the exponential decay of the power rails, a few power supplies may not be
designed to handle this short pulse condition. In this case, the power supply will not respond
to this event and never power back up. These power supplies would need to be unplugged and
re-plugged to bring the system back up. Power supplies not designed to handle this condition
must have their power rails decay to a certain voltage level before they can properly respond
to PS_ON. This level varies with affected power supply.
• The ATX spec does not specify a minimum pulse width on PS_ON de-assertion, which means
power supplies must be able to handle any pulse width. This issue can affect any power supply
(beyond ATX) with similar PS_ON circuitry. Due to variance in the decay of the core power
rails per platform, a single board or chipset silicon fix would be non-deterministic (may not
solve the issue in all cases).
• The platform designer must ensure that the power supply used with the platform is not
affected by this issue.
9.9 LAN Layout Guidelines
The ICH2 provides several options for integrated LAN capability. The platform supports several
components depending on the target market. These guidelines use the 82562ET to refer to both the
82562ET and 82562EM. The 82562EM is specified in those cases where there is a difference.
Table 36. Integrated LAN Options
LAN Connect
Component
Connection Features
82562EM Advanced 10/100 Ethernet AOL* & Ethernet 10/100 Connection
82562ET 10/100 Ethernet Ethernet 10/100 Connection
82562EH 1Mb HomePNA* LAN 1Mb HomePNA* connection
Intel developed a dual footprint for 82562ET and 82562EH to minimize the required number of
board builds. A single layout with the specified dual footprint will allow the OEM to install the
appropriate LAN connect component to meet the market need. Design guidelines are provided for
each required interface and connection. Refer to Figure 117 and Table 37. LAN Design Guide
Section Reference.
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