Intel Pentium 4

Memory Interface Routing
R
Intel
®
Pentium
®
4 Processor / Intel
®
850 Chipset Family Platform Design Guide 97
Note: This compensation factor is based on the Intel 850 chipset customer reference board (CRB) stack-
up.
The lengthening of the clock signals, to compensate for their trace velocity change, only applies to
routing between the MCH and first RIMM connector. The clock signals should be matched in
length to the RSL signals between RIMM connectors.
Equation 5. Clock Trace Length Calculation for Stripline
300/400 MHz RDRAM technology:
CFM/CFM# Clock Length = Nominal RSL Signal Length (package + board)* 1.009
(1)
CTM/CTM# Clock Length = Nominal RSL Signal Length (package + board)* 1.009
(1)
533 MHz RDRAM technology:
CFM/CFM# Clock Length = Nominal RSL Signal Length (package + board)* 1.009
(1)
CTM/CTM# Clock Length = Nominal RSL Signal Length (package + board)* 1.009 + 45
pS
(1)
Note: This compensation factor is based on the Intel 850 chipset customer reference board (CRB) stack-
up.
The lengthening of the clock signals, to compensate for their trace velocity change, only applies to
routing between the MCH and first RIMM connector. The clock signals should be matched in
length to the RSL signals between RIMM connectors.
6.1.2.3.1 Non-Differentially Routed Clocks – 533 MHz Rambus RDRAM* Technology
For 533 MHz (PC1066) RDRAM technology, if the clock signals CTM/CTM# and CFM/CFM#
are not routed differentially, then an additional 10pS per inch should be added to CTM/CTM# -
MCH to first RIMM connector guideline only.