Intel Pentium 4 User Manual

Memory Interface Routing
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Intel
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Pentium
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4 Processor / Intel
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850 Chipset Family Platform Design Guide 101
Figure 63. Bottom Layer CTAB with RSL Signal Routed on the Same Layer (Ceff = 1.35 pF)
The CTAB can be implemented on the multiple layers to minimize routing and space constrains.
Figure 64 issues the use of CTABs on the top and bottom layer for bottom layer RSL and clocking
signals routed between RIMM connectors.
Figure 64. Bottom Layer CTABs Split Across the Top and Bottom Layer to Achieve an Effect
Ceff ~1.35 pF

Intel Pentium 4 Specifications

General

Architecture	x86
Core Count	1
Microarchitecture	NetBurst
Manufacturer	Intel
Core Names	Willamette, Northwood, Prescott, Cedar Mill
Virtualization Technology	No
Release Date	November 20, 2000
Clock Speed	1.3 GHz to 3.8 GHz
FSB Speed	400 MHz to 1066 MHz
Socket	Socket 423, Socket 478, LGA 775
Introduced	2000
Product Line	Pentium
Front Side Bus	400 MHz to 1066 MHz
Hyper-Threading	Yes (Prescott and later)
64-bit Support	Yes (Prescott and later)
Instruction Set	MMX, SSE, SSE2, SSE3
Discontinued	2008
Process Technology	180 nm, 130 nm, 90 nm, 65 nm
L2 Cache	256 KB, 512 KB, 1 MB, 2 MB
Lithography	180 nm, 130 nm, 90 nm, 65 nm
L1 Cache	8 KB