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Pen
tiu
m
®
Pr
o Family
Developer
’
s Manual
V
olume 1
:
Specificatio
ns
NOTE
: The
Penti
u
m
®
Pr
o Famil
y
Devel
oper
’
s
Ma
nual
co
nsists of three
books:
Spec
ificatio
ns
,
Order
Number 242
690;
Program
mer
’
s Ref
erence
Manua
l
, Order Number 24269
1; and t
he
Opera
ting Sys
tem W
ri
ter
’
s Guide
,
Order Number 242692
.
Ple
ase
refer to all three volume
s when eva
lua
ting your design needs.
1996
2
Table of Contents
Main Page
Default Chapter
3
Table of Contents
3
Chapter 1 Component Introduction
17
APIC and Bus Controller
18
Figure 1-1. the Pentium ® Pro Processor Integrating the CPU, L2 Cache
18
Bus Features
19
Bus Description
20
System Design Aspects
21
Efficient Bus Utilization
21
Multiprocessor Ready
21
Data Integrity
22
System Overview
22
Terminology Clarification
23
Compatibility Note
25
Chapter 2 Pentium ® Pro Processor Architecture Overview
26
Processor
26
Figure 2-1. Three Engines Communicating Using an Instruction Pool
28
Full Core Utilization
29
Figure 2-2. a Typical Code Fragment
29
Pentium ® Pro Processor Architecture Overview 2.1. Full Core Utilization
29
The Pentium ® Pro Processor Pipeline
30
Figure 2-3. the Three Core Engines Interface with Memory Via Unified Caches
30
The Fetch/Decode Unit
31
Figure 2-4. Inside the Fetch/Decode Unit
31
The Dispatch/Execute Unit
32
Figure 2-5. Inside the Dispatch/Execute Unit
33
The Retire Unit
34
The Bus Interface Unit
34
Figure 2-6. Inside the Retire Unit
34
Architecture Summary
35
Figure 2-7. Inside the Bus Interface Unit
35
Chapter 3 Bus Overview
36
Signal and Diagram Conventions
37
Signaling on the Pentium Pro Processor Bus
38
Figure 3-1. Latched Bus Protocol
39
Pentium ® Pro Processor Bus Protocol Overview
40
Transaction Phase Description
40
Bus Transaction Pipelining and Transaction Tracking
42
Bus Transactions
43
Data Transfers
44
Line Transfers
45
Part Line Aligned Transfers
45
Partial Transfers
45
Pro Processor Bus Line Transfers
45
Table 3-1. Burst Order Used for Pentium
45
Signal Overview
46
Execution Control Signals
46
Table 3-2. Execution Control Signals
46
Arbitration Phase Signals
48
Table 3-3. Arbitration Phase Signals
48
Request Signals
49
Table 3-4. Request Signals
49
Table 3-5. Transaction Types Defined by Reqa#/Reqb# Signals
50
Table 3-6. Address Space Size
51
Table 3-7. Length of Data Transfer
51
Table 3-8. Memory Range Register Signal Encoding
52
Table 3-9. DID[7:0]# Encoding
52
Table 3-10. Special Transaction Encoding on Byte Enables
53
Table 3-11. Extended Function Pins
53
Error Phase Signals
54
Snoop Signals
54
Table 3-12. Error Phase Signals
54
Table 3-13. Snoop Signals
55
Response Signals
56
Table 3-14. Response Signals
56
Data Phase Signals
57
Table 3-15. Transaction Response Encodings
57
Table 3-16. Data Phase Signals
57
Error Signals
58
Table 3-17. Error Signals
58
Compatibility Signals
59
Table 3-18. PC Compatibility Signals
59
3.4.10. Diagnostic Signals
60
Table 3-19. Diagnostic Support Signals
60
3.4.11. Power, Ground, and Reserved Pins
61
Chapter 4 Bus Protocol
62
Arbitration Phase
63
Protocol Overview
63
Bus Signals
64
Internal Bus States
65
Symmetric Arbitration States
65
Figure 4-1. BR[3:0]# Physical Interconnection
65
Agent ID
66
Rotating ID
66
Symmetric Ownership State
66
Request Stall Protocol
66
Request Stall States
67
BNR# Sampling
67
Arbitration Protocol Description
67
Symmetric Arbitration of a Single Agent after RESET
67
Figure 4-2. Symmetric Arbitration of a Single Agent after RESET
68
Signal Deassertion after Bus Reset
69
Figure 4-3. Signal Deassertion after Bus Reset
69
Delay of Transaction Generation after Reset
70
Figure 4-4. Delay of Transaction Generation after Reset
70
Symmetric Arbitration with no LOCK
71
Figure 4-5. Symmetric Bus Arbitration with no LOCK
71
Symmetric Bus Arbitration with no Transaction Generation
72
Bus Exchange Among Symmetric and Priority Agents with no LOCK
73
Figure 4-6. Symmetric Arbitration with no Transaction Generation
73
Figure 4-7. Bus Exchange Among Symmetric and Priority Agent with no LOCK
74
Symmetric and Priority Bus Exchange During LOCK
75
Figure 4-8. Symmetric and Priority Bus Exchange During LOCK
75
BNR# Sampling
76
Figure 4-9. BNR# Sampling after RESET
76
Figure 4-10. BNR# Sampling after ADS
77
Symmetric Agent Arbitration Protocol Rules
78
Reset Conditions
78
Bus Request Assertion
78
Ownership from Idle State
78
Ownership from Busy State
79
Bus Parking and Release with a Single Bus Request
79
Bus Exchange with Multiple Bus Requests
79
Priority Agent Arbitration Protocol Rules
79
Reset Conditions
79
Bus Request Assertion
80
Bus Exchange from an Unlocked Bus
80
Bus Release
80
Bus Lock Protocol Rules
80
Bus Ownership Exchange from a Locked Bus
80
Request Phase
80
Bus Signals
81
Request Phase Protocol Description
81
Figure 4-11. Request Generation Phase
81
Request Phase Protocol Rules
82
Request Generation
82
Request Phase Qualifiers
82
Error Phase
82
Bus Signals
83
Snoop Phase
83
Snoop Phase Bus Signals
83
Table 4-1. HIT# and HITM# During Snoop Phase
83
Snoop Phase Protocol Description
84
Normal Snoop Phase
84
Figure 4-12. Four-Clock Snoop Phase
84
Stalled Snoop Phase
85
Figure 4-13. Snoop Phase Stall Due to a Slower Agent
85
Snoop Phase Protocol Rules
86
Snoop Phase Results
86
Valid Snoop Phase
87
Snoop Phase Stall
87
Snoop Phase Completion
87
Snoop Results Sampling
87
Response Phase
87
Response Phase Overview
87
Bus Signals
88
Response Phase Protocol Description
88
Response for a Transaction Without Write Data
88
Table 4-2. Response Phase Encodings
88
Figure 4-14. RS[2:0]# Activation with no TRDY
89
Write Data Transaction Response
90
Figure 4-15. RS[2:0]# Activation with Request Initiated TRDY
90
Implicit Writeback on a Read Transaction
91
Figure 4-16. RS[2:0]# Activation with Snoop Initiated TRDY
91
Implicit Writeback with a Write Transaction
92
Figure 4-17. RS[2:0]# Activation after Two TRDY# Assertions
92
Response Phase Protocol Rules
93
Request Initiated TRDY# Assertion
93
Snoop Initiated TRDY# Protocol
93
TRDY# Deassertion Protocol
93
RS[2:0]# Encoding
94
RS[2:0]#, RSP# Protocol
94
Data Phase
95
Data Phase Overview
95
Bus Signals
95
Data Phase Protocol Description
95
Simple Write Transfer
95
Simple Read Transaction
96
Figure 4-18. Request Initiated Data Transfer
96
Implicit Writeback
97
Figure 4-19. Response Initiated Data Transfer
97
Full Speed Read Partial Transactions
98
Figure 4-20. Snoop Initiated Data Transfer
98
Relaxed DBSY# Deassertion
99
Figure 4-21. Full Speed Read Partial Transactions
99
Full Speed Read Line Transfers (same Agent)
100
Figure 4-22. Relaxed DBSY# Deassertion
100
Full Speed Write Partial Transactions
101
Figure 4-23. Full Speed Read Line Transactions
101
Full Speed Write Line Transactions (same Agents)
102
Figure 4-24. Full Speed Write Partial Transactions
102
Figure 4-25. Full Speed Write Line Transactions
103
Data Phase Protocol Rules
104
Valid Data Transfer
104
Request Initiated Data Transfer
104
Snoop Initiated Data Transfer
104
Chapter 5 Bus Transactions and Operations
105
Bus Transactions Supported
106
Bus Transaction Description
107
Memory Transactions
107
Figure 5-1. Bus Transactions
107
Memory Read Transactions
110
Memory Write Transactions
110
Memory (Read) Invalidate Transactions
110
Reserved Memory Write Transaction
111
I/O Transactions
111
Request Initiator Responsibilities
112
Addressed Agent Responsibilities
112
Non-Memory Central Transactions
112
Request Initiator Responsibilities
113
Central Agent Responsibilities
113
Observing Agent Responsibilities
113
Interrupt Acknowledge Transaction
113
Branch Trace Message
114
Special Transactions
114
Shutdown
115
Flush
115
Halt
115
Sync
116
Flush Acknowledge
116
Stop Grant Acknowledge
116
SMI Acknowledge
116
Deferred Reply Transaction
117
Request Initiator Responsibilities (Deferring Agent)
117
Addressed Agent Responsibilities (Original Requestor)
118
Reserved Transactions
118
Bus Operations
118
Implicit Writeback Response
118
Memory Agent Responsibilities
119
Requesting Agent Responsibilities
119
Transferring Snoop Responsibility
120
Figure 5-2. Response Responsibility Pickup Effect on an Outstanding Invalidation
120
Deferred Operations
121
Response Agent Responsibilities
122
Requesting Agent Responsibilities
123
Figure 5-3. Deferred Response Followed by a Deferred Reply to a Read Operation
123
Locked Operations
124
Split] Bus Lock
125
Chapter 6 Range Registers
126
Introduction
127
Range Registers and Pentium
127
Pro Processor Instruction
127
Execution
127
Pro Processor
127
Memory Type Descriptions
129
UC Memory Type
129
WC Memory Type
129
WT Memory Type
129
WP Memory Type
130
WB Memory Type
130
Chapter 7 Cache Protocol
131
Line States
132
Memory Types, and Transactions
133
Memory Types: WB, WT, WP, and UC
133
Bus Operations
133
Naming Convention for Transactions
134
Chapter 8 Data Integrity
135
Error Classification
137
Pentium ® Pro Processor Bus Data Integrity Architecture
137
Bus Signals Protected Directly
137
Data Integrity 8.1. Error Classification
137
Table 8-1. Direct Bus Signal Protection
138
Bus Signals Protected Indirectly
139
Unprotected Bus Signals
141
Time-Out Errors
141
Hard-Error Response
142
Bus Error Codes
142
Parity Algorithm
142
Pentium Pro Processor Bus Ecc Algorithm
142
Error Reporting Mechanism
142
MCA Hardware Log
142
MCA Software Log
142
IERR# Signal
143
BERR# Signal and Protocol
143
Figure 8-1. BERR# Protocol Mechanism
143
BINIT# Signal and Protocol
144
Figure 8-2. BINIT# Protocol Mechanism
145
Speculative Errors
146
Fatal Errors
146
Figure 8-3. Pentium Pro Processor Errors
146
Pentium Pro Processor Time-Out Counter
147
Chapter 9 Configuration
148
Description
149
Figure 9-1. Hardware Configuration Signal Sampling
149
Output Tristate
150
Built-In Self Test
151
Data Bus Error Checking Policy
151
Response Signal Parity Error Checking Policy
151
AERR# Driving Policy
151
AERR# Observation Policy
151
BERR# Driving Policy for Initiator Bus Errors
151
BERR# Driving Policy for Target Bus Errors
152
Bus Error Driving Policy for Initiator Internal Errors
152
9.1.10. BERR# Observation Policy
152
9.1.11. BINIT# Driving Policy
152
9.1.12. BINIT# Observation Policy
152
9.1.13. In-Order Queue Pipelining
152
9.1.14. Power-On Reset Vector
153
9.1.15. FRC Mode Enable
153
9.1.16. APIC Mode
153
9.1.17. APIC Cluster ID
153
Table 9-1. APIC Cluster ID Configuration for the Pentium
153
9.1.18. Symmetric Agent Arbitration ID
154
Table 9-2. BREQ[3:0]# Interconnect
154
Figure 9-2. BR[3:0]# Physical Interconnection
155
9.1.19. Low Power Standby Enable
156
Table 9-3. Arbitration ID Configuration
156
Clock Frequencies and Ratios
157
Clock Frequencies and Ratios at Product Introduction
158
Software-Programmable Options
158
Table 9-8. Pentium ® Pro Processor Power-On Configuration Register Arbitration ID Configuration
160
Chapter 10 Pentium ® Pro Processor Test Access Port (Tap)
161
Figure 10-1. Simplified Block Diagram of Pentium
162
Interface
163
Accessing the Tap Logic
163
Figure 10-2. TAP Controller Finite State Machine
163
10.2.1. Accessing the Instruction Register
165
Figure 10-4. Operation of the Pentium
166
10.2.2. Accessing the Data Registers
167
Instruction Set
167
Figure 10-5. TAP Instruction Register Access
167
Pro Processor TAP
168
Table 10-1. 1149.1 Instructions in the Pentium
168
Data Register Summary
169
10.4.1. Bypass Register
169
10.4.2. Device ID Register
169
Table 10-2. TAP Data Registers
169
10.4.3. bist Result Boundary Scan Register
170
10.4.4. Boundary Scan Register
170
Reset Behavior
170
Table 10-3. Device ID Register
170
Table 10-4. TAP Reset Actions
171
Chapter 11 Electrical Specifications
172
The Pentium Pro Processor Bus and Vref
173
Pro Processor Bus and Vref
173
Figure 11-1. GTL+ Bus Topology
173
Power Management: Stop Grant and Auto Halt
174
Power and Ground Pins
174
Decoupling Recommendations
175
Figure 11-2. Transient Types
175
Vccs Decoupling
176
GTL+ Decoupling
176
11.4.3. Phase Lock Loop (PLL) Decoupling
176
Bclk Clock Input Guidelines
177
11.5.1. Setting the Core Clock to Bus Clock Ratio
177
Figure 11-3. Timing Diagram of Clock Ratio Signals
177
Figure 11-4. Example Schematic for Clock Ratio Pin Sharing
178
11.5.2. Mixing Processors of Different Frequencies
179
Voltage Identification
179
Table 11-1. Voltage Identification Definition
179
Jtag Connection
180
Signal Groups
181
11.8.1. Asynchronous Vs. Synchronous
181
Table 11-2. Signal Groups
182
Pwrgood
183
11.10. Thermtrip
183
Figure 11-5. PWRGOOD Relationship at Power-On
183
11.11. Unused Pins
184
11.12. Maximum Ratings
184
Table 11-3. Absolute Maximum Ratings 1
185
11.13. D.C. Specifications
186
Table 11-4. Voltage Specification
186
Table 11-5. Power Specifications 1
187
Table 11-6. GTL+ Signal Groups D.C. Specifications
188
Gtl+ Bus Specifications
189
Table 11-8. GTL+ Bus D.C. Specifications
189
11.15. A.C. Specifications
190
Table 11-9. Bus Clock A.C. Specifications
190
Table 11-10. Supported Clock Ratios
191
Table 11-11. GTL+ Signal Groups A.C. Specifications
191
Table 11-12. GTL+ Signal Groups Ringback Tolerance
192
Table 11-13. 3.3V Tolerant Signal Groups A.C. Specifications
192
Figure 11-6. 3.3V Tolerant Group Derating Curve
193
Table 11-14. Reset Conditions A.C. Specifications
193
Table 11-15. APIC Clock and APIC I/O A.C. Specifications
194
Table 11-16. Boundary Scan Interface A.C. Specifications
195
Figure 11-7. Generic Clock Waveform
196
Figure 11-8. Valid Delay Timings
196
Figure 11-9. Setup and Hold Timings
197
Figure 11-10. lo to Hi GTL+ Receiver Ringback Tolerance
197
Figure 11-11. FRC Mode BCLK to PICCLK Timing
198
Figure 11-12. Reset and Configuration Timings
198
Figure 11-13. Power-On Reset and Configuration Timings
199
Figure 11-14. Test Timings (Boundary Scan)
199
11.16. Flexible Motherboard Recommendations
200
Figure 11-15. Test Reset Timing
200
Table 11-17. Flexible Motherboard (FMB) Power Recommendations
200
Temperature
200
Chapter 12 Gtl+ Interface Specification
201
System Specification
202
12.1.1. System DC Parameters
203
Figure 12-1. Example Terminated Bus with GTL+ Transceivers
203
Table 12-1. System DC Parameters
204
12.1.2. Topological Guidelines
205
12.1.3. System AC Parameters: Signal Quality
205
Table 12-2. System Topological Guidelines
205
Figure 12-2. Receiver Waveform Showing Signal Quality Parameters
206
Table 12-3. Specifications for Signal Quality
206
Ringback Tolerance
207
Figure 12-3. Standard Input Lo-To-Hi Waveform for Characterizing Receiver
208
Figure 12-4. Standard Input Hi-To-Lo Waveform for Characterizing Receiver
208
12.1.4. AC Parameters: Flight Time
209
Figure 12-5. Measuring Nominal Flight Time
210
Figure 12-6. Flight Time of a Rising Edge Slower than 0.3V/Ns
211
Figure 12-7. Extrapolated Flight Time of a Non-Monotonic Rising Edge
212
Figure 12-8. Extrapolated Flight Time of a Non-Monotonic Falling Edge
212
General Gtl+ I/O Buffer Specification
213
12.2.1. I/O Buffer DC Specification
213
12.2.2. I/O Buffer AC Specification
214
Table 12-4. I/O Buffer DC Parameters
214
Table 12-5. I/O Buffer AC Parameters
215
Output Driver Acceptance Criteria
216
Figure 12-9. Acceptable Driver Signal Quality
217
Figure 12-10. Unacceptable Signal, Due to Excessively Slow Edge after
217
12.2.3. Determining Clock-To-Out, Setup and Hold
218
Clock-To-Output Time, TCO
218
Figure 12-11. Test Load for Measuring Output AC Timings
219
Figure 12-12. Clock to Output Data Timing (TCO)
219
Minimum Setup and Hold Times
220
Figure 12-13. Standard Input Lo-To-Hi Waveform for Characterizing Receiver
221
Figure 12-14. Standard Input Hi-To-Lo Waveform for Characterizing Receiver
221
Receiver Ringback Tolerance
222
System-Based Calculation of Required Input and Output Timings
223
Calculating Target TCO-Max, and TSU-Min
223
Package Specification
224
12.3.1. Package Trace Length
224
12.3.2. Package Capacitance
225
Ref8N Network
225
Figure 12-15. Ref8N Topology
226
12.4.1. Ref8N HSPICE Netlist
227
Chapter 13 Tolerant Signal Quality Specifications
229
Overshoot/Undershoot Guidelines
230
Ringback Specification
231
Figure 13-1. 3.3V Tolerant Signal Overshoot/Undershoot and Ringback
231
Table 13-1. Signal Ringback Specifications
231
Settling Limit Guideline
232
Chapter 14 Thermal Specifications
233
Thermal Parameters
234
14.1.1. Ambient Temperature
234
14.1.2. Case Temperature
234
Figure 14-1. Location of Case Temperature Measurement (Top-Side View)
235
Figure 14-2. Thermocouple Placement
235
14.1.3. Thermal Resistance
236
Figure 14-3. Thermal Resistance Relationships
236
Thermal Analysis
237
Figure 14-4. Analysis Heat Sink Dimensions
237
Table 14-1. Case-To-Ambient Thermal Resistance
237
Table 14-2. Ambient Temperatures Required at Heat Sink for 29.2W and 85° Case
238
Table 14-3. Ambient Temperatures Required at Heat Sink for 40W and 85° Case
238
Chapter 15 Mechanical Specifications
239
Dimensions
240
Figure 15-1. Package Dimensions-Bottom View
241
Figure 15-2. Top View of Keep out Zones and Heat Spreader
242
Table 15-1. Pentium ® Pro Processor Package
242
Pinout
243
Figure 15-3. Pentium ® Pro Processor Top View with Power Pin Locations
243
Table 15-2. Pin Listing in Pin # Order
244
Table 15-3. Pin Listing in Alphabetic Order
248
Chapter 16 To O Ls
253
Analog Modeling
253
In-Target Probe for the Pentium Pro Processor (Itp)
253
16.2.1. Primary Function
254
16.2.2. Debug Port Connector Description
254
16.2.3. Debug Port Signal Descriptions
254
Table 16-1. Debug Port Pinout
254
16.2.4. Signal Notes
255
Figure 16-1. GTL+ Signal Termination
255
Signal Note 1: RESET#, Prdyx
256
Signal Note 2: DBRESET
256
Signal Note 3: POWERON
256
Signal Note 4: DBINST
256
Signal Note 5: TDO and TDI
256
Signal Note 6: PREQ
256
Signal Note 7: TRST
257
Signal Note 8: TCK
257
Figure 16-2. TCK with Daisy Chain Configuration
257
Table 16-2. TCK Pull-Up Value
257
Signal Note 9: TMS
258
Figure 16-3. TCK with Star Configuration
258
16.2.5. Debug Port Layout
259
Figure 16-4. Generic MP System Layout for Debug Port Connection
260
Signal Quality Notes
261
Debug Port Connector
261
Figure 16-5. Debug Port Connector on Primary Side of Circuit Board
261
Using Boundary Scan to Communicate to the Pentium Pro Processor
262
Figure 16-6. Hole Layout for Connector on Primary Side of Circuit Board
262
Figure 16-8. Pentium ® Pro Processor-Based System Where Boundary Scan Is Used
263
Chapter 17 Overdrive ® Processor Socket Specification
264
Introduction
265
17.1.1. Terminology
265
Mechanical Specifications
266
Figure 17-1. Socket 8 Shown with the Fan/Heatsink Cooling Solution, Clip Attachment Features and Adjacent Voltage Regulator Module
266
Vendor Contacts for Socket 8 and Header 8
267
17.2.2. Socket 8 Definition
267
Socket 8 Pinout
267
Figure 17-2. Overdrive ® Processor Pinout
267
Socket 8 Space Requirements
268
Figure 17-3. Overdrive ® Processor Envelope Dimensions
269
Socket 8 Clip Attachment Tabs
271
Figure 17-4. Space Requirements for the Overdrive
271
Overdrive ® Voltage Regulator Module Definition
272
Overdrive ® VRM Requirement
272
Overdrive ® VRM Location
272
Overdrive ® VRM Pinout
272
Figure 17-5. Header 8 Pinout
273
Overdrive Vrm Space Requirements
274
Table 17-2. Header 8 Pin Reference
274
Functional Operation of Overdrive
275
Fan/Heatsink Power (V CC5 )
275
Upgrade Present Signal (UP#)
275
Processor
275
Figure 17-7. Upgrade Presence Detect Schematic - Case 1
276
17.3.3. BIOS Considerations
277
Overdrive ® Processor CPUID
278
Common Causes of Upgradability Problems Due to BIOS
278
Overdrive ® Processor Electrical Specifications
278
Specifications
278
Overdrive ® Processor D.C. Specifications
279
Table 17-4. Overdrive ® Processor D.C. Specifications
279
Overdrive ® VRM D.C. Specifications
280
Overdrive ® Processor Decoupling Requirements
280
Table 17-5. Overdrive ® VRM Specifications
280
17.4.3. A.C. Specifications
281
Thermal Specifications
281
Overdrive ® Processor Cooling Requirements
281
Fan/Heatsink Cooling Solution
281
17.5.2. OEM Processor Cooling Requirements
281
A.C. Specifications
281
Overdrive ® VRM Cooling Requirements
282
17.5.4. Thermal Equations and Data
282
Criteria for Overdrive Processor
283
Table 17-7. Overdrive ® Processor Thermal Resistance and Maximum Ambient
283
17.6.1. Related Documents
284
17.6.2. Electrical Criteria
284
Overdrive ® Processor Electrical Criteria
284
Table 17-8. Electrical Test Criteria for Systems Employing Header 8
285
Pentium ® Pro Processor Electrical Criteria
286
17.6.3. Thermal Criteria
286
Table 17-10. Electrical Test Criteria for All Systems
286
Overdrive ® Processor Cooling Requirements
286
Overdrive ® Processor Cooling Requirements (Systems Testing Only)
287
Voltage Regulator Modules (Systems Employing Aheader 8 Only)
287
17.6.4. Mechanical Criteria
287
Table 17-11. Thermal Test Criteria
287
Table 17-12. Mechanical Test Criteria for the Overdrive
287
Overdrive ® VRM Clearance and Airspace Requirements
288
17.6.5. Functional Criteria
288
Software Compatibility
288
BIOS Functionality
288
Table 17-13. Functional Test Criteria
288
17.6.6. End User Criteria
289
Qualified Overdrive Processor Components
289
Visibility and Installation
289
Jumper Configuration
289
BIOS Changes
289
Documentation
289
Upgrade Removal
289
Appendix Asignals Reference
291
Alphabetical Signals Reference
291
A[35:3]# (I/O
291
A20M# (I
292
Ads# (I/O
292
A.1.2. A20M# (I)
292
Aerr# (I/O
293
A.1.4. Aerr# (I/O)
293
A.1.5. Ap[1:0]# (I/O)
294
Table A-1. ASZ[1:0]# Signal Decode
294
A.1.8. Bclk (I)
295
Table A-2. ATTR[7:0]# Field Descriptions
295
A.1.10. Berr# (I/O)
296
A.1.12. Bnr# (I/O)
297
A.1.15. Bpri# (I)
298
Table A-4. BR0#(I/O), BR1#, BR2#, BR3# Signals Rotating Interconnect
298
A.1.17. Breq[3:0]# (I/O)
299
Table A-5. BR[3:0]# Signal Agent Ids
299
A.1.18. D[63:0]# (I/O)
300
A.1.21. Den# (I/0)
301
A.1.24. Drdy# (I/O)
302
Table A-6. DID[7:0]# Encoding
302
A.1.26. Exf[4:0]# (I/O)
303
Table A-7. EFX[4:0]# Signal Definitions
303
A.1.29. Frcerr(I/O)
304
A.1.31. Ierr# (O)
305
A.1.34. Intr (I)
306
Table A-8. LEN[1:0]# Signals Data Transfer Lengths
306
A.1.37. Lock# (I/O)
307
A.1.41. Pwr_Gd (I)
308
Table A-9. Transaction Types Defined by Reqa#/Reqb# Signals
308
A.1.43. Reset# (I)
309
A.1.45. Rs[2:0]#(I)
310
Table A-10. Transaction Response Encodings
310
A.1.46. Rsp# (I)
311
A.1.49. Splck# (I/O)
312
A.1.55. Trdy# (I)
313
A.2. Signal Summaries
314
Table A-12. Input Signals
315
Table A-13. Input/Output Signals (Single Driver
315
Table A-14. Input/Output Signals (Multiple Driver)
317
Intel Literature Centers
319
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Intel Pentium Pro Family Specifications
General
Brand
Intel
Model
Pentium Pro Family
Category
Computer Hardware
Language
English
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